John Brummer Email & Phone Number

Santa Clara, Ca, Us

Participated in the design and implementation of R&D CMOS sensors on rolling shutter and global shutter readoutsImplemented various blocks testing new algorithms for noise and power reduction, speed improvementRTL integration using inherited databasesAnalog design support.

Scottsdale, Arizona, Us

• Participated in the design and tape-out of 8,10,14,18,20 and 25 MegaPixel CMOS based color sensors. • Digital lead role for 8Mp and 14Mp color sensors, owning design from conception through post production, leading a design / verification team spread over several international sites, uncluding a 8Mp 5x4 array imager sensor development with successful completion.• RTL integration using a shared database maintained by independent internationally distributed design groups.• Support analog design, physical implementation, product and application / product Engineering and customers.• Definition, Verilog RTL design, integration and verification of pixel timing generation, offset / dark current compensation, channel balance, row wise temporal and column fixed pattern noise correction, gradient compensation, gain and dither, CRC self-checking logic for automotive applications, one-time programmable memory control logic and various other control and design-for-test blocks, as well as top level architecture and interface specifications. • Architecture support and maintenance.

Rochester, New York, Us

• Studied, designed, verified and hardware-characterized imaging algorithms (Auto exposure, Offset Correction, Defect Correction, Special effects, Contrast/brightness/saturation) • Independently converted a 2Megapixel monochrome automotive camera-on-a chip device to color, acted as design lead through post production.• Wrote functional test benches and tested block-level RTL (Verilog-XL / VCS).• Top level clock tree design, integration and Physical Synthesis (Physical / power Compiler)• Static Timing Analysis of post-route top-level 0.18um CMOS netlists (Primetime).• Top-level design-for-test integration (Tetramax).• Formal verification (Formality / Conformal) • Interface with and support Analog Design, Physical Implementation, Product and Test Engineering.• Studied and modeled CMOS imaging array architectures and array timing (4T/4S, 3T).

Munich, Bavaria, De

• Architecture, design, and implementation using standard-cell and transistor-level logic on monochrome gray-scale OLED display drivers with programmable driving schemes. • Designed custom dual-port static memory at transistor level, with perpendicular port addressing and asynchronous (non-clocked) logic. Integrated custom functions in memory periphery at transistor-level to reduce overall chip size. Analog parasitic extraction, corner simulation (Spectre / Spice) and supervision of static ram layout (Cadence environment).• Participated in the definition of top-level chip architecture and wrote top-level functional test benches.• Specified, designed, implemented and tested cascadable high-power color graphic LED drivers using high-speed custom serial interfaces and uniformity calibration circuitry with on-chip EEPROM.• Integrated and tested JTAG on a 1Ghz optical fiber mux/demux chipset.• Periodically managed a design group during various design phases, including tape-out, with timely completion and coordination between team members. Management duties supplemented regular design tasks.

Developed ASIC and FPGA implementations of data encryption algorithms used in commercial broadcast and defense systems.Successfully supervised, designed, prototyped (in FPGA) and tested a 240Mhz mixed-signal CODEC ASIC with a unique encryption algorithm in 1.5um CMOS technology using VHDL.Developed and deployed a software and hardware toolset embedding unique hardware codes into ACTEL FPGA netlists prior to fuse-secured programming.Completed several ACTEL FPGA designs for encrypted television broadcasting, on time and with success.

Pretoria, Gauteng, Za

Designed digital imaging devices and developed far-infrared InSb and Silicon Photodiode Sensors.Researched, developed and characterized Silicon photo sensors and related processing techniques.Developed a highly accurate multi-layer wafer bonded light mask using layered, anisotropically etched Silicon for large-area quadrant PIN photodiodes and ultraviolet sensors used for spatial orientation in satellite systems.Designed, manufactured and tested various Silicon Avalanche photo detectors, including a 350V RAPD structure used in high-precision laser-distance measurement equipment.Developed software for analyzing the physical semiconductor processes inside avalanche photodiodes and aid in the design of photodiodes in general, improving parameters like quantum efficiency, signal to noise ratio, speed and wavelength responsivity.Participated in a start-up venture (SST) and participated in, managed and completed several projects, including a 1kx1k CMOS readout chip for a InSb infrared detector array, a 512x1 CMOS photocurrent amplifier array for HgCdTl sensors, a composite wind-flow sensor, and various Silicon PIN, PN and other photodiode structures and modules.

Masters Of Engineering, Electrical And Electronics Engineering

Bachelor Of Science (B.Sc.), Electronic Engineering