John Callaghan Email & Phone Number

Project Architect/Engineer, Individual Contributor -- Box, board, and chip -level design from modeling/analysis to schematic/BOM, fab/assembly, RTL/drivers and DV/test.► Active safety (24/77 GHz automotive radars) – radar capture/playback systems, HW/SW specifications, Xilinx SoC (Zynq, UltraScale+, Petalinux), IP integration, DFT, FCT, *FMEA, precision.

Design and bring-up of metrology mixed analog-digital boards and FPGAs. Altera Cyclone FPGA designs using Verilog in Quartus and simulation with ModelSim, board designs via Mentor DxDesigner and PADS. Mixed signal ST Micro ARM core CPU-based boards incorporating FPGAs and ADC, DAC, analog, digital and power circuits. Performed FPGA coding and simulation.

Santa Clara, California, US

► Implemented Intel instructions into new generation of ARC processor IP core, Intel ► Designed and verified in simulation a high speed LVDS differential DDR serial to parallel ADC interface for Zynq7000 FPGA to be used on a miniature Transponder for drone applications ► Implemented DOLBY audio in Altera Cyclone FPGA and PCIe for high speed data into an.

► Resolved several customer issues through redesign, simulation and implementation of communications protocols such as ATM and T1/E1 in Xilinx Virtex2 Pro and Altera Stratix FPGA ► Designed test circuitry to verify an audio/video ASIC in a Virtex4 FPGA before tape out. Designed an external USB interface for the FPGA test card saving significant time and.

►To IronBridge Networks, MA: Member of ASIC design team for a telecommunications data switch ASIC. The designs utilized an 8b/10b serdes, pipelined interface with asynchronous FIFOs and Arbitration logic.►To Stratus, MA: Designed and verified a fault tolerant clock recovery ASIC utilizing a Verilog environment.►To Sun Microsystems, MA: Project Lead.