John Callaghan Email & Phone Number

Project Architect/Engineer, Individual Contributor -- Box, board, and chip -level design from modeling/analysis to schematic/BOM, fab/assembly, RTL/drivers and DV/test.► Active safety (24/77 GHz automotive radars) – radar capture/playback systems, HW/SW specifications, Xilinx SoC (Zynq, UltraScale+, Petalinux), IP integration, DFT, FCT, *FMEA, precision timing architectures, visualization tools, liaison with subcontractors, self-test, diagnostics, production workarounds, analysis with MCU/DSP, FPGA/CPLD, JTAG; PLM, PTC, Jira, Python► proposals for Free Space Optics links, MOEMS based spectrometer, adaptive optics (astron.), underwater UV meter► added pulsed and stepped-FM research modes and digital datalink to an automotive radar with embedded TI ARM MCU and Spartan-3 FPGA (DCM to <50ps), using C/Matlab/Verilog/Perl.► evaluation/test of IP cores for C-Cor DVB digital-TV FEC/scrambler/encoder (J83)► enhancements/speedup of Analogics multichannel ultrasound scanner memory subsystems► turnkey design/development of zlib compression engine using Orcad, CAM, V2Pro, Linux► design/test of custom 1080 Mbps weather radar datalink based on 1000Base-T / PoE► design/DV of Lucent Microelectronics “SuperMapper/UltraMapper” ASIC, including synchronization, PDH data cross-connect, and built-in test features VHDL/Synopsys► DV of Avici Systems Terabit Switch Router packet scheduler / multicast engine (VCS/Vera)► design/test of full rate OC-12 ATM 'flyby' pattern-matching engine for Net2Net Corp. ORCA► other projects including: HyperTransport v1.04 SES core, Lucent LUC3M08 10/100 Ethernet repeater ASIC, printer-sharing ASIC, ...

Design and bring-up of metrology mixed analog-digital boards and FPGAs. Altera Cyclone FPGA designs using Verilog in Quartus and simulation with ModelSim, board designs via Mentor DxDesigner and PADS. Mixed signal ST Micro ARM core CPU-based boards incorporating FPGAs and ADC, DAC, analog, digital and power circuits. Performed FPGA coding and simulation test-benches, created PCB schematics, drove layout, brought up boards, etc. Simulated analog circuits with LTSPICE. Board environment featured high voltage arcing withstand requirements and control of high value capital equipment.

Santa Clara, California, Us

► Implemented Intel instructions into new generation of ARC processor IP core, Intel ► Designed and verified in simulation a high speed LVDS differential DDR serial to parallel ADC interface for Zynq7000 FPGA to be used on a miniature Transponder for drone applications ► Implemented DOLBY audio in Altera Cyclone FPGA and PCIe for high speed data into an Altera Arria FPGA for a hand held Audio Test Equipment ► Integrated internal and external IP’s and ASIC redesign for emulation and validation in Xilinx Virtex7 2000 FPGA. Design flow generation and scripting for Synplify/Vivado. ROM insertion flow development and implementation in Verilog and Python ► Designed Xilinx/Altera FPGAs for Biometric data collection systems for SHARP Laboratories

► Resolved several customer issues through redesign, simulation and implementation of communications protocols such as ATM and T1/E1 in Xilinx Virtex2 Pro and Altera Stratix FPGA ► Designed test circuitry to verify an audio/video ASIC in a Virtex4 FPGA before tape out. Designed an external USB interface for the FPGA test card saving significant time and money ► Researched, selected, integrated and tested PCI Express IP with in-house modules for GPIO, HDLC and RS232 in an FPGA. Designed a video broadcast PCIe test card for the FPGA ► Designed several wrappers to verify a Verilog Network Processor in multiple Xilinx Virtex2 and Altera Stratix FPGA’s. Design involved Ethernet, XSI bus, PCI Express interfaces► Designed, verified and implemented several modules to integrate third party IP’s for WiMAX Wireless Communication System in Altera Stratix-II FPGA ► Designed and developed hardware including PCB’s for a variety of highly cost sensitive consumer items ► Designed and implemented an FPGA for an Absolute Head Tracker involving video image processing for severely handicapped in Spartan3 FPGA

►To IronBridge Networks, MA: Member of ASIC design team for a telecommunications data switch ASIC. The designs utilized an 8b/10b serdes, pipelined interface with asynchronous FIFOs and Arbitration logic.►To Stratus, MA: Designed and verified a fault tolerant clock recovery ASIC utilizing a Verilog environment.►To Sun Microsystems, MA: Project Lead, architect, and design of a proprietary PC emulation ASIC. This included the Management and coordination of three design groups located in MA, CA and CO. Designed an FPGA CPU and Cache controller for a PC hardware emulation product. Verification Engineer to verify a PCI bus controller.►To Sequoia Systems Inc., MA: Design of a check-point and resume recovery FPGA.Narad Networks Incorporated, Westford, MA 2000-2003►Project Lead, architect, and designer of a proprietary 100Mb packet switch with QoS Queuing ►Designed packet switch FPGA including; Power PC 405 CPU, SRAM, and broadband modem interfaces ►Designed a 100Mb switch to Serial Optical Fiber module utilizing Xilinx Virtex II FPGAHigh Speed Solutions, Hudson, MA 1999-2000►Lead designer for the digital portion of a prototype ASIC to demonstrate a modulated 4bit/symbol I/O►The company was purchased for this technology Howrey & Simon, Washington, DC 1998-1999Blakely, Sokoloff, Taylor & Zarfman LLP, San Jose,CA►Technical expert of a successful patent litigation►To Stratus, MA: Designed and verified a fault tolerant clock recovery ASIC utilizing a Verilog environment.►To Sequoia Systems Inc., MA: Design of a check-point and resume recovery FPGA.►To Sun Microsystems, MA: Project Lead, architect, and design of a proprietary PC emulation ASIC. This included the Management and coordination of three design groups located in MA, CA and CO. Designed an FPGA CPU and Cache controller for a PC hardware emulation product. Verification Engineer to verify a PCI bus controller.