As a IP Verification Engineer,architect and develop UVM based highly reusable test benches on IPlevels,develop RTL behavior Reference Models and verification components.Responsible：-MMU Verification.-RBC Verification.-Developed reference model.

As a SOC Verification Engineer,integrate and develop the verification environment,ensure thecompleteness of chip verification,signed off coverage.Responsible：-5G Baseband Processors subsystem verification.-developed Low Power verification.-built UVM testbench and debuged testcases.