John M. Email & Phone Number

Bethesda, MD, US

Bethesda, MD, US

Palo Alto, California, US

Responsible for implementation and design of NPU subsystems.

Palo Alto, California, US

Lead implementation responsibility for a low power EMI mitigation subsystem. Co-designed with architect and implemented a firmware programmable Microcontroller based low power EMI mitigation circuit. The proprietary fixed-point arithmetic circuit utilized frequency domain detection, acquisition and tracking and adaptive time domain cancellation. Created a.

San Jose, California, US

Co-designed a scalable PID based servo controller in a Xilinx FPGA that controls a 4-axis robot to cost reduce Quantum’s Scalar i500 tape library. The controller utilizes a Xilinx MicroBlaze embedded processor to interpret system commands and hardware assists implementing the PID loop, trajectory generation and motion control hardware for four concurrent.

Note: This position was formerly at SiTera and before that, originally at Fusion Micromedia. Vitesse acquired SiTera in April 2000.Co-designed the Lookup Coprocessor for the 5 million gate IQ2000 network processor using Verilog and Synopsys DC. Designed the instruction queue structure, arbitration, bus protocol, and master/slaves for a proprietary 12.8.

For networking reference only. SiTera was acquired by Vitesse, refer to activities at Vitesse Semiconductor for full description.

Provided design verification services for two 700K gate ASICs bridging three cache coherent quad-processor Intel Pentium Pro busses. Developed regression and directed random tests using Pentium Pro BFMs and proprietary verification tools.

Austin, TX, US

Composed and synthesized various VHDL modules implementing 40 MHz, 0.6 um CMOS mixed signal PRML read channel devices. Co-developed and utilized a mixed signal simulation environment using Epic TimeMill and Model Tech VHDL simulator.

Designed 40 MHz, 75K gate, 0.6 um CMOS ASIC using Verilog design entry and Synopsys synthesis. Device implemented a SPARC Mbus compliant bus Level 3 cache bridge for a Dual CPU board

Designed a 200 MHz, 20K transistor full custom ASIC for a single event upset (SEU) radiation hardened CPU module using Mentor Graphics schematic capture tools, IC and discrete wire board physical design tools and Spice. Implemented in Vitesse 1.75 um GaAs process. Also implemented 16x9 Microwire (tm) board that connected 7 full custom chips and memory to.

Served as Technical Leader for design and integration of four unique 24”x24” circuit boards into a very large scale DSP system. Designed three 50 MHz ECL standard cell ASICs and a 24"x24" circuit board implementing reconfigurable DSP logic (up to 27 add-multiply-accumulate functions). Also redesigned a 16"x24" multiport memory circuit board implementing.

Bsee, Electrical Engineering, Microprocessors, Dsp, Digital Design

Pre-Engineering Studies, 60 Hours, Pre-Engineering