John Pabisz Email & Phone Number

San Diego, Ca, Us

San Diego, Ca, Us

San Diego, California, Us

• Responsible for implementing a UVM verification environment to support AXI, AHB and APB host buses, and I/O protocols including UART, I3C, CAN, Soundwire, eMMC and GPIO.• Create a randomization solution for an I/O pin mux with complex configuration constraints for connecting I/O functions to pads.• Wrote an inverse pin mux in verilog, to decode complex design mux configuration and route GPIO pins to agent interfaces, as well as innovating a random constraint model to randomize pin mux configuration.• Wrote perl scripts to generate UVM RAL code from textual register description files.• Integrated non-UVM 3rd-party I3C and CAN VIP into the UVM environment: Analyzed VIP for best course of action. Wrote Perl scripts to convert SystemVerilog task-based tests into UVM sequences and generate a UVM test. Converted the VIPs from supporting one VIP instance to multiple concurrently executing VIPs. • Wrote verilog top level, UVM env, high level configuration sequences, integrated layered sequences to support higher level test benches, wrote BASH simulation and regression scripts. Wrote python cvs code release script.• Fixed multitude of issues in a transition from Mentor Incisive to Cadence Xcellium simulations.• Analyzed incomplete DMA controller design for I2S sound, and prescribed rtl changes for completion. • Developed eMMC DV sub-environment using Avery VIP.• Debugged analog pad model issues.Developed C-based testcases to verify elements of ARM Cortex based SoC design• Coded interrupt service routines and self-checking diagnostic• Developed peripheral stimulus: Timers, GPIO, Watchdog, DMA, and UART• Debugged RTL design issues using Cadence SimVision waveforms• Debugged C-code issues using internal registers and assembly listings• Using GIT for revision history

Austin, Texas, Us

PCIe Root-Complex Design Verification (Remote Individual Contributor)* Performed technical responsibilities, including test planning, scoreboard and ingress stimulus design and implementation, transaction layer and physical layer testing, supporting framework development, nightly regression triage.* Tested complex design supporting Gen4, up to 16 lanes, dynamically reconfiguring to be multi-port host, AER capability, power management capability, INT-X capability, proprietary downstream port containment.* Implemented UVM testbench using proprietary common framework, creating abstract API layer to support any endpoint agent, using primarily Synopsys and Cadence models interchangeably and in tandem. Wrote single scoreboard with analysis ports taking input from PCIe fabric, host bus, RAL register layer, and reset agent. Wrote extensive error status and error message prediction class, verifying fatal, non-fatal and correctable errors.* Wrote sequences and tests, specifically verifying ingress pipeline, including dma requests, pio responses, TLP messages, and TLPs generated internally by host. Derived vendor sequences for power management. Injected errors both internally from fabric, verifying correct behavior of each layer of PCIe stack.* Used lightweight Agile process, including scrum sessions, code review, and weekly code release.

Austin, Texas, Us

PCIe Root-Complex Silicon Bringup and Validation 2014 – 2015* Developed validation scripts (in Perl) for link training, gathering statistics, testing, and debugging embedded PCIe cluster inside of UltraSPARC SoC.* Developed I/O-core, co-simulation testbench (in SystemVerilog), allowing lab-validation scripts to be simulated with pre-silicon RTL.* Integrated host interface unit, data management unit, PCIe unit, SerDes, and 3rd-party endpoint model, as well as clock, reset, and initialization support code; debugged all hardware issues impeding successful PCIe link-up status. Coded header files (in C) for CSR address translation.* Employed file I/O solution, implementing virtual channel for inter-process communication.* Participated in cross-team, multi-site, bring-up effort, completing PCIe link training in silicon.* Debugged several, time-sensitive, high-profile post-silicon PCIe issues during system bring-up, keeping time-to-market scheduling on track.* PCIe subsystem is in a production SOC with no show-stopper bugs.

Austin, Texas, Us

Physical Control Sublayer module verification (verification lead).* Verified design featuring gen3 and up to 16 lanes, proprietary SerDes / PCS interface, Intel PIPE interface, embedding micro-code to control link equalization, 28nm.* Authored and executed testplan and schedule, managed regressions and releases, analyzed code covered, and mentored junior engineer.* Designed and implemented new testbench in straight systemverilog. (Project constraints necessitated rapid implementation of lightweight testbench.)* Developed tests for symbol lock, block lock, loss of lock, clock drift, bit-slip, skip insertion, variable length skip ordered sets, equalization, IP micro-code execution block, PIPE error conditions, mid-test resets, proprietary CSR testing.* Testbench exhibited high RTL code coverage, finding bugs dating back 2 generations; module is part of production SOC with no show-stopper bug escapes.

Austin, Texas, Us

PCIe Root-complex subsystem verification (verification lead).* Led verification team, testing design enhancements of previous product: expansion from 8 to 16 lanes, new configurable link-width paradigm, vendor change for PCS and SerDes, ~1M gates in PCIe, 28nm.* Managed regressions and releases, communicating weekly status and participating in project leadership meetings, analyzing code coverage.* Saved significant development time by enhancing testbench design from prior project.* Improved test-writing interface, adding multiple test thread support and cohesive debug interface across all components.* Modified existing 1-port scoreboard, dynamically supporting N-number of independent ports. (This extensibility is now being used in current projects.)* Modified existing PCIe transactor, supporting link-width up to x16 and embellished equalization checking.* Wrote verilog top module wiring, verifying firmware device initialization flow, integrating third party PCS and SerDes, designing top-down random initialization flow.* Ported transaction layer tests, developing new tests for gen3 equalization, I/O performance, trace buffer debug feature, and LTSSM history debug feature.* PCIe subsystem is in production SOC with no show-stopper bugs.

Palo Alto, Ca, Us

• PCIe Root-complex subsystem verification.• FPGA PCIe Diagnostic endpoint verification.• Cache coherency hub chip verification.• PCIe host bridge subsystem verification.• Multi-I/O chip verification (PCI, Sbus, Ethernet, Ebus IP, host-side IP), Verification lead.• Video chip verification, Verification lead.• Programmable interrupt controller (8259) and timer (8253) module verification.

Palo Alto, Ca, Us

Hardware Quality Assurance and Reliability.• Calculated reliability predictions (IEEE 1413).• Set up systems to demonstrate MTBF.• Wrote C programs to control multiple test equipment that were GPIB capable (IEEE 488).• Configured lab networks in SunOS.• Wrote Cshell programs to collect diagnostic data.• Designed an 8-to-1 KVM switch for lab use.

Master Of Science (M.S.), Computer Engineering

Bachelor Of Science (B.S.), Electrical And Electronics Engineering

Pre-Engineering

Various M.S. Prerequisite Courses Through Sitn, Computer Software Engineering