ASIC design for embedded KVM server applications. Front end design, verification/prototyping of Video Compression engine in SOC ASICs (Faraday) and FPGA’s (Xilinx) for Vertiv/Avocent Server Appliance products. Co-inventor on multiple Video Compression Patents.

Front end design, simulation, implementation and validation of FLIR Video processing algorithms (VHDL) in Xilinx Virtex2 FPGA parts.

Worked on design teams for 2 large standard Cell GPUs. Performed Front end design/debug/verification/synthesis (VHDL) for multiple Pixel Engine sub-modules. Authored/maintained top level synthesis makefile for Pixel Engine. Timing Closure/ECO specialist for base/metal tape-outs (COT). Wrote instructional guide and conducted training class for Back End ECO/Timing closure.

FPGA(Xilinx)/PCB design of multiple Hi-MAC product Telco Modules

FPGA(Altera)/PCB design of Flight Simulator Calligraphic Module

VHDL design/synthesis of modules for 2 CMOS ASICs (Comanche/F-22). Designed "Frame Grabber" card for Quickturn emulation of F-22 video display.