Staff Design Engineer
Minato-Ku, Tokyo, Jp
PROFESSIONAL EXPERIENCEOperating Systems : Linux, UNIX, DOS, MS-WINDOWS, SUNOSScripting Languages : TCL, Perl, tcsh, and vendor-specific environmentsASIC Design Tools : Synopsys Primetime, ICC, ICV Synopsys/Magma Talus/Blast Physical Design Tool Suite Cadence Virtuoso Layout Suite Mentor Graphics Calibre Physical Verification Suite (DFM/LVS/DRC/ERC) Apache Redhawk Power Analysis TSMC reference flows and methodologies Global Foundries reference flows and methodologies Proprietary ESD failure analysis suite Proprietary Signal Integrity suite• Support all aspects of physical design implementation of ASICs from customer RTL through GDSII• Full chip and hierarchical block physical integration with custom internal and 3rd party embedded processors, IP and IO interfaces (e.g. ARM, PLL, USB, ADC, DAC, PCI Express (PCIe), DDR, Serdes, SRAM, DRAM)• Work closely with customers to vet full chip and hierarchical block timing constraints• Low power and multi voltage analysis, implementation and timing closure• Dynamic and static power analysis and IRDROP at full chip and hierarchical block level• Clock tree synthesis (CTS) and implementation• Multi-mode and multi-corner (MMMC) static timing analysis (STA) and implementation• Signal integrity (SI) analysis including noise analysis and on-chip variation (OCV)• Performed Electro Static Discharge (ESD) analysis to recommend solutions to meet foundry standards• TCL script creation and improvement to automate processes and methodologies• ECO and Post-Mask ECO implementation• Calibre (DFM/DRC/LVS/ERC) analysis and correction• Collaborate with 3rd party tool vendors to customize flows and methodologies• Document and present design reviews internally and externally throughout implementation process• Experience leading and collaborating with colleagues and contractors across multi-international, geographically distributed teams
