John Schiff Email & Phone Number

Austin, TX, US

Santa Clara, California, US

Armonk, New York, NY, US

• In this role I program managed a highly matrixed, world-wide team of over 100 engineers in delivering a proprietary high-speed interface (32Gbs) and a 50Gbs Nvidia NVLink3 design in first Global Foundries then Samsung.
• Completed a complete overhaul of the execution team and schedules to recover one year of lost development as a result of IBM switching from Global Foundries to Samsung’s 7nm technology o Troubleshot and redefined.
• Successfully drove the global team to ramp up and begin execution in 1.5 months in order to deliver two new test chips in the new Samsung 7nm technologyo First test chip two months after the technology reseto Second.
• Ramped-up and performed coaching on three new managers in project management
• Successfully delivered all product data on time with the highest level of risk mitigation.Additional Information- Teams located in Austin TX, Rochester MN, Burlington VT, Raleigh NC, Poughkepsie NY, and Bangalore.

Armonk, New York, NY, US

• In this role I program managed a highly matrixed, world-wide team of over 90 engineers to deliver a 16Gbs IBM proprietary interface, 19.2 and 25Gbs Nvidia NVLink2 interfaces, and a DDR4 interface, all using Global.
• Incorporated the addition of a new ASIC team of over 40 engineers to map a DDR4 design in one-year due to new product requirements
• Created new execution methodologies to streamline Mixed Signal Verification by using AMS behavioral models and schematic netlists in Event Sim (NCSim), Cycle Sim (MESA/Fusion), and Accelerator Environments to.
• Drove the adoption of a common delivery methodology to simultaneously provide complete custom design data to each P and Z programs
• Worked closely with 3rd party vendors for resource and capital acquisitions on short-term and long-term needs

Armonk, New York, NY, US

• In this role I managed a team of over 25 electrical engineers delivering 5.4 to 10Gbs IBM proprietary interfaces to the P and Z programs
• Worked with chip upline leadership to develop High Level Project Milestones then worked with team leads to develop detailed execution schedules
• Routinely reported up-line as well as overall team on current execution status: Identifying key dependencies, shortages, and risks
• Implemented many new development methodologies to reduce resource demand as well as reduce risk:o Analog design automation using genetic algorithms to automate the tuning of routine analog circuits o Created a static.

Armonk, New York, NY, US

• Designed High Speed Analog IO Circuits to be integrated into the (Elastic Interface 1, 2, and 3) designs for the Power4, 5, 6 projects, as well as the Z-series mainframes and Apple G4 processor chips.
• Managed the technical design, simulation and delivery of high speed interfaces, overseeing the work of 5 circuit designers.
• Established and ensured all designs met specifications.
• Ensured all physical designs adhered to chip tools and methodologies. Patents
• Modable Dynamic Terminator for High Speed Digital Communications 2005-06-14 US6906550
• Logic line driver system for providing an Optimal Driver Characteristic 2007-05-01 US7212035

Las Cruces, NM, US

Conducted experiments on low power VLSI/MEMS designs and maintained laboratory NT workstations.

Pasadena, CA, US

Conducted space qualification and reliability research on MEMs devices.

Randolph AFB, TX, US

• 4th Space Warning Squadron 01/93—12/95Space Systems Instructor
• Conducted training on satellite systems and served as Technical Advisor to maintenance personnel. AN/MSQ118 Maintenance Crew Chief 07/90—01/93
• Supervised 10 technicians to handle the maintenance, repair and operations of Air Force Mobile Early Warning System. 1936th Communication Squadron 03/89—07/90Defense Meteorological Satellite Program Team Member
• Maintained, repaired, and handled operations of space systems communication equipment.

Bsee, Vlsi

Bachelor Of Science - Bs, Electrical And Electronics Engineering

Architecture

Education record