John Schiff Email & Phone Number

Austin, Tx, Us

Austin, Tx, Us

Santa Clara, California, Us

Armonk, New York, Ny, Us

In this role I program managed a highly matrixed, world-wide team of over 100 engineers in delivering a proprietary high-speed interface (32Gbs) and a 50Gbs Nvidia NVLink3 design in first Global Foundries then Samsung 7nm technology. The scope of the delivery included all skill areas of silicon development specializing in mixed signal/analog architectures. My daily activities included status gathering, analyzing potential execution risks, finding technical solutions, and communicating to not to just my team, but also up-line executives. Key Highlights:• Completed a complete overhaul of the execution team and schedules to recover one year of lost development as a result of IBM switching from Global Foundries to Samsung’s 7nm technology o Troubleshot and redefined project resource sizings, high-level milestones, and execution schedules/metricso Expanded team from 80 to 120 people in three months by hiring a mix of experienced professional engineers along with working with 3rd Party Vendors to bring in Contractors• Successfully drove the global team to ramp up and begin execution in 1.5 months in order to deliver two new test chips in the new Samsung 7nm technologyo First test chip two months after the technology reseto Second test chip five months after technology reset o All chips successfully debugged and characterized in time for product first design pass• Ramped-up and performed coaching on three new managers in project management• Successfully delivered all product data on time with the highest level of risk mitigation.Additional Information- Teams located in Austin TX, Rochester MN, Burlington VT, Raleigh NC, Poughkepsie NY, and Bangalore India.- Interfaces range from sub-1Gbs to 50Gbs. -NRZ based (Source Synchronous and CDR) Interface Architectures -Single Ended Interface Architectures -NVLink 7nm Technologies running at 50Gbs

Armonk, New York, Ny, Us

In this role I program managed a highly matrixed, world-wide team of over 90 engineers to deliver a 16Gbs IBM proprietary interface, 19.2 and 25Gbs Nvidia NVLink2 interfaces, and a DDR4 interface, all using Global Foundries’ 14nm technology to the P and Z programs simultaneously. The scope of the delivery included all skill areas of silicon development specializing in mixed signal/analog architectures. I also managed a team of over 20 engineers. My daily activities included status gathering, analyzing potential execution risks, finding technical solutions, communicating to not to just my team, but also up-line executives, giving performance feedback and coaching for all direct reports.Key Highlights:• Incorporated the addition of a new ASIC team of over 40 engineers to map a DDR4 design in one-year due to new product requirements• Created new execution methodologies to streamline Mixed Signal Verification by using AMS behavioral models and schematic netlists in Event Sim (NCSim), Cycle Sim (MESA/Fusion), and Accelerator Environments to drastically increase coverage from mid-50% range to over 95%• Drove the adoption of a common delivery methodology to simultaneously provide complete custom design data to each P and Z programs• Worked closely with 3rd party vendors for resource and capital acquisitions on short-term and long-term needs

Armonk, New York, Ny, Us

In this role I managed a team of over 25 electrical engineers delivering 5.4 to 10Gbs IBM proprietary interfaces to the P and Z programs• Worked with chip upline leadership to develop High Level Project Milestones then worked with team leads to develop detailed execution schedules• Routinely reported up-line as well as overall team on current execution status: Identifying key dependencies, shortages, and risks• Implemented many new development methodologies to reduce resource demand as well as reduce risk:o Analog design automation using genetic algorithms to automate the tuning of routine analog circuits o Created a static timing analysis of analog blocks methodology by creating analog timing rules (NDRs) to expand timing coverage and drastically decreasing black box usage

Armonk, New York, Ny, Us

• Designed High Speed Analog IO Circuits to be integrated into the (Elastic Interface 1, 2, and 3) designs for the Power4, 5, 6 projects, as well as the Z-series mainframes and Apple G4 processor chips.• Managed the technical design, simulation and delivery of high speed interfaces, overseeing the work of 5 circuit designers. • Established and ensured all designs met specifications. • Ensured all physical designs adhered to chip tools and methodologies. Patents• Modable Dynamic Terminator for High Speed Digital Communications 2005-06-14 US6906550 • Logic line driver system for providing an Optimal Driver Characteristic 2007-05-01 US7212035 • Adjustable Switchpoint Receiver 2007-04-10 US7202723 • Method for reducing cross-talk induced source synchronous bus clock jitter 2008-06-03 US7382151 • Pulldown driver with gate protection for legacy interfaces 2008-11-25 US7457091 • Method for reducing cross-talk induced source synchronous bus clock jitter 2009-01-13 US7477068• Slew rate control for driver circuit 2009-04-21 US7521968• System and method for switching digital circuit clock net driver without losing clock pulses 2010-07-06 US7752480• System and Method for Converting Between CML Signal Logic Families 2010-10-26US7821300• Configurable Pre-emphasis Driver with Selective Constant and Adjustable Output Impedance Modes 2011-02-15 US7888968Publications:• IBM Power5 bus designs for on- and off-module connections. 13th Topical Meeting on Electrical Performance for Electronic Packaging

Las Cruces, Nm, Us

Conducted experiments on low power VLSI/MEMS designs and maintained laboratory NT workstations.

Pasadena, Ca, Us

Conducted space qualification and reliability research on MEMs devices.

Randolph Afb, Tx, Us

4th Space Warning Squadron 01/93—12/95Space Systems Instructor• Conducted training on satellite systems and served as Technical Advisor to maintenance personnel. AN/MSQ118 Maintenance Crew Chief 07/90—01/93• Supervised 10 technicians to handle the maintenance, repair and operations of Air Force Mobile Early Warning System. 1936th Communication Squadron 03/89—07/90Defense Meteorological Satellite Program Team Member• Maintained, repaired, and handled operations of space systems communication equipment.

Bsee, Vlsi

Bachelor Of Science - Bs, Electrical And Electronics Engineering

Architecture

Education record