John She Email & Phone Number

San Jose, Ca, Us

Saratoga, California, Us

+ Design 2-layer flex PCB with 25um line space for both packaged IC and bumped die. + In charge of PCB vendor selection. Family with stack up, material, cost and EM simulation.+ Manage DFM of IC-Package-PCB with both package, assembly suppliers and system team.+ Developed flex PCB assembly process for Augmented Reality Contact lens with micro LED, sensors, controller, Power IC. First ever Contact Lens with display inside with 5G Radio.+ Developed 1st ever aggressive 25um pitch stud bump flip chip process for bare die IC on flex PCB using ACP (anisotropic conductive paste) with partner Jabil blue sky center.+ Ramp up flex assembly yield and address critical failure using various FA methods (Xray, cross section, thermal imaging, SEM); + Family with JDDEC IPC spec and PCB, IC reliability qualification items and process.

San Jose, Ca, Us

+ Designed and manufactured multiple generations of 3 axis, 6 axis inertial motion sensor in QFN LGA, as well as 7 axis, 9 axis combo sensor with pressure and compass sensor in SIP LGA. Enable stand-alone pressure sensor with extreme high bond line thickness in cavity LGA with metal lid. And introduced Automotive Grade Motion sensor in Pre Mold Cavity QFN with LCP liquid crystal polymer lid.+ Work with cross-functional teams and lead package integration and architecture efforts.+ Perform regular OSAT audit to ensure high quality, high yield for extreme high volume sensor.+ Work with 3rd party and OSAT (ASE AMKOR LINGSEN JCET UTAC) to bring up packaging solution from concept to HVM. Drive industry with advanced package solutions and specs.+ Expert in advanced packaging technologies, deliver high performance interconnects in various form factor, thermo-mechanical, reliability, and cost constraints. Bring up 1st smallest 6 axis Motion Sensor with Cu Pillar WLCSP on un-even MEMS surface.

+ Successfully validated and characterized Mix Signal SOC devices on bench and ATE.+ Manager Sr. Product Engineer and Sr. Test Engineering team for new product introduction. Refine test methodology for test time reduction and yield improvement.+ Manage IC supply chain: wafer, package and test vendors: TSMC UTAC UNISEM, provide cost module. Work with local FA lab Riga, EAG, FIB lab for RMA failure analysis.

+ Successfully validated and characterized two analog audio noise cancellation devices on bench.+ Responsible for ATE development using Eagle ETS364 Analog/Mix signal Tester, evaluate Teradyne J750 as test platform for next generation devices. Familiar with RF Analog module and test method. + Manage high volume production yield with Galaxy Yield Analysis tool.

San Jose, California, Us

+ Develop Capacitive Touch IC test method on Teradyne J750 system.+ Perform in depth analysis of Capacitive Touch IC ATE Test Methodology. Reduce overall test time for development and production ramp-up+ Lead the package design for very large die with small package size 3x3mm QFN, solving the time to market issue by using innovative package solution at ASE and UTAC

Us

+ Define test methodology (DFT/DFM), test plan for Capacitive Finger Print Device.+ Drive multiple projects simultaneously with foundries on mask design review; process data analysis; skew corner lot characterization. Worked with UMC on special top IMD layer CMP process integration into standard CMOS flow and qualifying the process.+ Strong knowledge with package development flow and good relationship with package vendors(ASE/Amkor/ASAT/GPAT); bring up both short term globing package for silicon debug and high volume molding package which using film over mold system (TOWA).

Irvine, Ca, Us

+ Analysis package mechanical, thermal and electrical performance, recommend product marketing team on package selection. Work closely with Package Vendor ASE, AMKOR.+ Develop Bench level test methodology for Mix Signal High Speed CMOS product SerDes. Perform first Silicon debug and characterization. + Work with product/design team define test platform, test strategy for High Speed 3Gbps 10Gbps Transceiver and Switch Fabric Chip sets.

Santa Clara, California, Us

+ Responsible for defining or developing and implementing ATE test hardware and software of flash memory. Including Read while Write feature, BURST feature, new multi-block Erase test method.