Manage analytic and data warehouse software tools focusing on manufacturing yield, quality, and optimization. Develop new tools and software solutions scalable and suitable for a high volume manufacturing environment spanning multiple vendors and subcons.

Test Engineering ManagementManaged the Test Engineering team to validate, characterize, qualify, and production release multiple mixed signal and display driver products in parallel. Drove DFT and DFM (manufacturing) initiatives for faster time to market, increased test coverage, shorter test times, and improved yield. Planned and executed first silicon validation activities spanning multiple offshore vendors to deliver tested samples in less than 2 weeks from fab-out. Initiated the purchase of the company's first production monitoring software (dataPower) and statistical analysis tools (JMP/SAS).Cost ReductionDelivered packaging road maps to reduce package cost while maintaining a lucrative body size for customers. Interfaced with package vendors to migrate production to newer package handling equipment for higher throughput and lower test cost. Wrote a test template library optimized for test time to provide a boiler plate for all test program development.Test Developer for New ProductDeveloped new test methodologies during the new product conception and design phase. Wrote pattern generation and conversion scripts from Verilog and WGL to Teradyne J750 format. Performed design simulations on test vectors for pre-silicon validation. Debugged, verified, and characterized tests during initial silicon evaluation. Automated statistical reports through scripting and standard Unix based tool sets.Product Engineering Support of New Chip Sale Business SegmentIntroduced new package options for existing products to aggressively compete in the space constrained market segment. Managed the introduction of a second packaging vendor, which included a site audit of the vendor and augmenting internal operations to support dual sourcing.Failure Analysis of RMA UnitsSegmented customer return units for new chip sale business segment. Consulted with internal and external support including wafer foundry to localize and identify the root cause of 307 returned units.

Test Program Developer for Phase Change Memory Worked with Design, Process, Yield, and Reliability Engineering groups to develop a comprehensive test program to support the data collection and characterization of new materials and cell configurations for a new PCM product on a low cost test system.Lead Programmer for SRAM Product Engineering Team: Developed from scratch fuse ECC, repair, and characterization tests, f-max, v-min, and Shmoo tests, as well as IDV characterization routines, data retention and read-disturb tests for custom SRAM cells on a new technology process.Primary Test Development Team Representative/Support for SRAM Yield Analysis Supported test chip yield analysis and defect segmentation by delivering and executing custom PBIST test patterns and characterization programs.SRAM Raster Owner Developed, validated, and maintained low-yield analysis programs and cell Vt characterization routines after initial first-silicon debug. Identified and corrected multiple defect isolation issues directly impacting yield and repair.High Parallelism Platform Test Developer Developed, validated, and maintained multiple tests including BIST self-diagnostics, program-erase Vt characterization, and ECC tests for a low cost ultra high parallelism and low pin count prototype test platform. Test developed required out of the box thinking and strong problem solving skills due to the platform architecture and cost constraints.