John A. Bielawski Email & Phone Number

• Currently designing analog circuit blocks using 0.18μ BCD process for IP library • Responsible for: CMOS bandgap regulator with second-order temperature correction, low-power CMOS comparator with programmable hysteresis, low-power CMOS op-amp, and supervising layout with mask designer

• Worked on Bluetooth 2.4GHz receiver for CMOS RFIC project using 0.18μ CMOS 7RF process at IBM. Responsible for: setting up EDA environment (Cadence Analog Artist and Synopsys CosmosSE, installed PDK, created device library, tested tools), designing CMOS bandgap regulator, low noise amplifier (LNA), top-level circuit assembly, and supervising layout with mask designer• Created, tested, and documented circuit design examples (CMOS bandgap regulator, LNA, differential and cascode amplifiers, two-stage op amp) for lab using Cadence Analog Artist and Synopsys CosmosSE schematic capture and simulation tools for CMOS RFIC and CMOS analog design classes• Designed tuned amplifier with capacitive neutralization as extra project for CMOS RFIC class• Instructor for Digital CMOS IC Design (0.25μ and below from an analog perspective) and Applied Electricity and Electronics courses. Developed lecture and lab for students

• Provided training for staff on Tanner software (S-Edit, T-Spice)• Created and documented Tanner circuit design labs for current mirror and CMOS bandgap regulator• Completed design and layout of plasma charge monitors using Tanner software (L-Edit)• Worked with marketing and prepared plasma charge monitor presentation for customer

RS485 bus transceivers - 0.8μ BICMOS and bipolar high-voltage processes• Lead design engineer for RS485 bus transceivers responsible for product design from concept to manufacturing release• Designed and simulated all transceiver circuits including: input translator, differential amplifier and comparator, bandgap regulator, voltage references, thermal shutdown, hysteresis, short-circuit current protection, I/O drivers, and ESD protection • Made extensive use of planet wafer fab runs (shared reticles among product groups containing test chips /circuits) to reduce overall development costs and time-to-market• Wrote code for DRC and LVS to accommodate symmetrical high-voltage output transistor which saved group several reticles and a fab run in the process resulting in improved time-to-market• Laid out circuits using Cadence software when no mask designers were available to keep project on schedule and within budget • Performed competitor product analysis and worked with marketing to determine key features and datasheet limits to ensure product would be acceptable to target customers and generate desired revenueLVDS receiver and driver - 0.35μ CMOS process• Re-designed bandgap regulator, power-up reset, ESD protection, and fixed latch-up on LVDS quad driver and receiver resulting in on-time fab transfer• Improved layout of ESD protection with performance improving to 7kV HBM and latch-up immunity to -2V resulting in a more desirable product for the customer and increased revenueHigh-speed RS485 transceiver with improved ESD - 0.8μ BiCMOS process• Project manager/engineering supervisor for RS485 ESD development• Worked with device technologist to develop and layout ESD test chip with mask designer• Led external testing lab effort for ESD support with test die passing 12kV HBM• Hired, supervised, mentored, and wrote reviews for junior design engineer• Supervised product engineer during characterization and bench testing

Switch Mode Power Conversion Fundamentals

Certificates, Analog Cmos Ic Design, Cmos Rf Ic Design

Bsee, Electrical Engineering

Engineering Management