John Carrillo Email & Phone Number

San Jose, Ca, Us

San Jose, Ca, Us

End client is confidential

Mountain View, California, Us

Bring-up and validation of blade product with four TSP devices, two Altera Agilex FPGAs, an Octeon processor, and an STM processor. Tested and validated several interfaces between devices using test diagnostics and custom scripts. Also bring-up and validation of an eight blade rack including power supply and fan control.

Menlo Park, Ca, Us

Emulation engineer for Cadence Palladium and Protium emulator products used for hardware emulation of SOC RTL for computational acceleration devices for artificial intelligence and machine learning applications incorporating CPU, memory, and switching IP.

Santa Clara, Ca, Us

Test engineer for GPU devices used for computational acceleration for artificial intelligence and machine learning applications incorporating proprietary serial switching and CPU IP along with GPU.

San Jose, Ca, Us

Security hardware group supporting development of network modules for security products.

San Jose, Ca, Us

Network switching and routing products group supporting development of new linecards and integrated routing products.

Sunnyvale, Ca, Us

Sustaining engineer for large core routing networking products

San Jose, Ca, Us

Optical DVT for evaluating and qualifying optical modules for various networking products.

San Jose, Ca, Us

Hardware Engineer developing manufacturing test platforms for the core router group products. Developed test platforms for four generations of products and working on next generation products. Worked closely with distributed engineering development team and offshore contract manufacturers. Involved in initial bring-up of prototype core router boards on manufacturing test platform using system diagnostics. Worked closely with distributed diagnostics and test development teams.

Fremont, Ca, Us

FPGA emulation platform using multiple FPGAs to map ASIC RTL for validation and debug of video processing ASIC for multi-monitor video outputs.

San Jose, Ca, Us

Sustaining engineer on 40G duobinary and DPSK transceivers with proprietary host interface. Optical transceiver boards include TI DSP and 860 PPC and Xilinx FPGAs. Designed modules for cost reduced Tunable Dispersion Compensation optical components with varying control mechanisms into existing design. Performed root cause analysis of field failures and worked with manufacturing test on improving yields.

Sunnyvale, Ca, Us

Design optical transponder modules for 100G CFP with 10 x10Gb interface and 1x TOSA and 4x ROSA optical modules. Worked on first 100G CFP specification incuding pinout. Worked closely with layout on stackup and escape pattern for routing of optical modules to straddle-mount edge connector with PCB maximum thickness requirement.

San Jose, California, Us

Hardware design of DUT and probe cards for in-house test system, demo cards and reference designs for camera module evaluation with integrated image sensor and image processing functions.

San Jose, Ca, Us

Board level design of validation and evaluation boards for IDT networking devices including PCI-Express switches, serial RapidIO routers, network processor offload TCAM routing chips, and high-speed serial XAUI interfaces. Logic design including component selection and schematic capture using Concept and Cadence Allegro, power analysis using Power Integrity, signal integrity using hspice and Cadence SI 630, and functional specifications including detailed design documents, block diagrams of implementation. Managed layout done by external PCB layout vendors. Develop in-house Cadence Concept design methodologies, development flow, and Concept libraries.

Santa Clara, California, Us

Design and development validation platforms for first silicon of new server chipsets for dual Xeon processors, including new high-speed FSB interconnects and dual FBDIMM memory channels.. Schematic entry using Cadence Viewlogic. Responsible for global clock distribution for validation board including processors, northbridge chipset, and FBDIMM memory interfaces. Cadence Allegro database for PCB layout. Routing constraints provided through in-house developed spreadsheet. Responsible for design of FBDIMM riser card with eight FBDIMM modules and two FBDIMM channel connectors on the validation board. Responsible for testing of high-speed FBDIMM memory interface and global system clocking.

Palo Alto, Ca, Us

CPU board development of Itanium2 processor and Intel 870 chipset for hardware fault-tolerant server.Design, development, and bring-up of CPU board with dual Itanium2 processors and 870 chipsets with lock-step comparison. Design, development, and bring-up of IO test board for verification of deterministic operation of Itanium2 processor and 870 chipset.

Palo Alto, Ca, Us

Design, development, and testing of memory module DIMMs for Sun microsystem's high end product line from workstations to servers. Represented Sun Microsystems at JEDEC standard setting meetings for next generation memory devices. Responsible for delivering Sun Microsystem's proprietary memory DIMM which met the divergent requirements of product teams across the product line. Qualification and testing of memory device and modules from memory suppliers.

Jp

Manager of memory subsystem development team for SPARC based workstation product. Team delivered four ASIC designs for memory controller and memory card designs. Team delivered motherboard PCB design and memory card design. Verification of subsystem design prior to tapeout of ASICs, Full-scan implementation with ATPG vector generation and BIST coverage of memory arrays. Bring-up and test in the lab of memory subsystem using BIST on memory controller and memory array.

System monitor board for initialization and control of large ECL-based supercomputer system that used Motorola microprocessor and ECL PLD devices. Full scan implementation required system monitor board to set initial state of entire system made up of ECL devices. Designed SPARC processor based mainframe using CMOS programmable logic devices for generic IO board.

Armonk, New York, Ny, Us

Designed ergonomic query terminal for distributed OS system with back-end hardware database server and file server connected through ethernet network using XNS protocol. Company was acquired by IBM.Metaphor Slide Show:

San Diego, California, Us

Designed RISC processor for hardware relational database server. The 10mips processor was implemented with ECL logic devices and ECL PLDs. It had a stripped down operating system running a single dedicated relational database program. Company was acquired by Teradata.

Mayville, Wi, Us

Designed desktop system with Intel 80286 processor and Digital Research CP/M and MP/M operating system in TAB Products DEC terminal enclosure.

Dallas, Tx, Us

Designed semiconductor memory card for network switching node for private computer timesharing network.

Developed memory card for minicomputer business system using Z80 microprocessors and QANTEL's BEST operating system. Designed data separator for 8-inch floppy drive and CRT controller for single-user system.http://www.qantel.com/

Phoenix, Arizona, Us

Process engineer for power transistor group. Developed high voltage polysilicon planar transistor power devices.

Mba, Management

Bs, Engineering (Semiconductor Physics)

Education record