20+ years experience in compiler engineering and ElectronicDesign Automation software development specializing in architecture and design of compiler infrastructure for programming and hardware description languages.Led the architecture and development of several compiling systems for C, C++, FORTRAN, including complete tool chains, for conventional and high-performance architectures. Architected and led the development of compilation infrastructure (static analysis and transformation) for RTL estimation in Verilog.Designed and developed compiler technology for a VLIW-based simulation engine for Verilog.Design and development of compiler and tool chain for custom DNN acceleration.I was a member of the technical staff at SDA Systems (Cadence).Specialties: Compiler architecture, multi-level IRs, static analysis, transformations, concurrent languages, runtime libraries, language design, HDL compilation, logic synthesis. C/C++, Haskell, ML, Python, C#, Java