John Schramm Email & Phone Number

St Joseph, Mi, Us

Implemented a digital low-pass filter in a Xilinx Spartan 3 FPGA. Filter equation realized in MATLAB, manually coded in VHDL, and simulated using Active HDL. Design also contains serial interfaces for ADC/DAC components as well as a PIC microcontroller.

Adapted ASIC design into a Xilinx FPGA development board. Designed and wrote required Verilog modules, complete with self-checking testbench, to interface and modify the ASIC HDL. System successfully exhibited ASIC design to customers before chip fabrication.Designed Verilog modifications for a new version of an FPGA demonstration system. Used Synopsys VCS and Xilinx ISE to deliver FPGA design. Coordinated with employees from other divisions around the U.S. to define and implement the changes.Automated a new testing environment by designing a LabVIEW application.

New York, Ny, Us

Worked in a team to create a software prototype of a phone for stockbrokers. Designed a C# XML interface to a database to run the PC side of the phone. Hand designed graphical user interface for software in Photoshop. Prototype was chosen to be expanded on by the company.

Supported ASIC validation team by designing LabVIEW software to automate the testing environment. The software controlled power supplies, multimeters, and oscilloscopes to acquire various data on the IC. Self-taught in LabView during design.

Bridgewater, Nj, Us

Researched nanotechnology applications for the eye care industry and presented findings to the VP of Strategy. Compiled nanotechnology information with eye care industry facts for inclusion into a corporate wide strategy document.Designed a new website for the Lean Manufacturing Initiative. The high profile site was deployed on the company's internal network to share information with 13,000+ employees.

Assisted in daughter board design for a newly acquired product line. Wrote VHDL code for the on-board FPGA to control timecode signal processing. The code was used in the final product shipped to customers in May 2006.Facilitated the reverse engineering of newly acquired bus level timing boards. Analyzed FPGA schematics and documented functionality of the legacy boards. Documentation was used to create newly redesigned versions of the boards.