Head Of Fpga
CurrentTrading platforms, apps architecture, strategies and data analytics. network, execution logics design from ground up and scale up.
May 2022 - Present
AeroLeads people directory · profile
Yi-Chen(John) Li Email & Phone Number
ASIC, FPGA & C++
at
BlackEdge Capital
LinkedIn matched
✓ Verified Jun 2026
3 data sources
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Current company
Role
ASIC, FPGA & C++
Location
Glen Rock, New Jersey, United States
Who is Yi-Chen(John) Li? Overview
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Quick answer
Yi-Chen(John) Li is listed as ASIC, FPGA & C++ at BlackEdge Capital, based in Glen Rock, New Jersey, United States. AeroLeads shows a matched LinkedIn profile for Yi-Chen(John) Li.
Yi-Chen(John) Li previously worked as Head of FPGA at Blackedge Capital and Snr HW Design Engineer at Vatic Labs. Yi-Chen(John) Li holds Electrical Engineering, Electronic & Computer Engineering from University Of Sydney.
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Email format at BlackEdge Capital
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BlackEdge Capital
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Profile bio
About Yi-Chen(John) Li
Lead design engineer for FPGA and ASIC with over 20 years of hands on, concept to tape-out experience. Designed SoCs for wireless signal processing and massive array of computer processors, shipped in commercial volume. Started and built Volant tradings pure FPGA trading platform and team for 4 years, wrote all layers of trading framework from scratch and managed rollout to multiple exchanges. Crafted Vatic's ultra low latency trading. Earlier work enabled Exablaze's 10G devices.Chrrently team leader in a high tech financial trading firm. Delivering world class acceleration in trading execution and computation.
Listed skills include Fpga, Asic, Digital Signal Processors, Systemverilog, and 24 others.
Current workplace
Yi-Chen(John) Li's current company
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9 roles · 26 years
Yi-Chen(John) Li work experience
A career timeline built from the work history available for this profile.
Snr Hw Design Engineer
Design and architect hybrid C++/FPGA HPC systems for financial application.Various R&D in HPC and Ai projects from core sim to production.
Jan 2018 - Jun 2021
Principal Design Engineer
FPGA team lead, design & implement HW tick to trade engines and low latency communication IPs & infrastructure. Fulfilled my promises to transform Volant into an all HW trading firm and ran this initiative into sizable returns, scaled the HW effort world wide and grew the team to many markets. Then bid farewell to pursuit new intelligence in the market.
Jan 2014 - Jan 2018
Senior Member Of Technical Staff
Wave is a new asynchronous start-up that focus on lower power, re-configurable computing fabric. We have internally developed a new logic family and tool flow plus a parallel processing architecture that addresses many challenges faced by today's ASIC world.I've taken on many roles in Wave and delivered results for our board & investors:- Coding TCAM in.
Jun 2012 - Dec 2013
Vp, Embedded Systems
Lead FPGA development for ultra low latency 10G networking and computing acceleration. Delivered and deployed complete 10G solution with cut-through processing. The product is now sold under the name EzxNIC by company Exablaze.http://www.wallstreetandtech.com/data-latency/faster-htfs-trading-under-a-microsecond/240162949Expertise gainedHW: PCIE TLP layer.
May 2011 - Jun 2012
Research Asic Engineer
Digital System Engineer for 60GHz/3+GBPS Wireless DBB system(Digital Baseband):Clockless Asynchronous IC research and design engineer.Work responsibilities:FPGA prototyping with RTL, Synthesis, embedded FW, processor and IP integration.System Model & Algorithm: Matlab/Simulink, C, System Studio. End to end system simulation with HW verification.
Nov 2007 - Mar 2011
Snr. Asic Design Engineer, Smts
Develop ASIC IP and products for 3GPP HSDPA/Rel7/LTE modem, such as turbo decoders, matrix solver and equalization receivers. Worked on HW architecture/design/verification, system modeling and algorithm development. HW architect for Agere's MB-OFDM UWB digital baseband project. In additionally, the web master for the Australian site.
Oct 2003 - Oct 2007
Snr. Asic Engineer, Smts
Develop IP and products for 3GPP HSDPA/Rel7/LTE modem. Worked on HW architecture/design/verification, system modeling and algorithm development. HW architect for Agere's MB-OFDM UWB digital baseband project. In additionally, the web master for the Australian site.
Oct 2003 - Jul 2007
Asic Design Engineer
Recruited by Dr. Chris Nicol into Lucent Bell Labs in 2000 to work on digital baseband for 3G UMTS basestation chips. Role included system requirements, HW/SW co-design and verification.
2000 - 2003
~3 yrs
1 education record
Yi-Chen(John) Li education
-
University Of Sydney
FAQ
Frequently asked questions about Yi-Chen(John) Li
Quick answers generated from the profile data available on this page.
What company does Yi-Chen(John) Li work for?
Yi-Chen(John) Li works for BlackEdge Capital.
What is Yi-Chen(John) Li's role at BlackEdge Capital?
Yi-Chen(John) Li is listed as ASIC, FPGA & C++ at BlackEdge Capital.
Where is Yi-Chen(John) Li based?
Yi-Chen(John) Li is based in Glen Rock, New Jersey, United States while working with BlackEdge Capital.
What companies has Yi-Chen(John) Li worked for?
Yi-Chen(John) Li has worked for Blackedge Capital, Vatic Labs, Volant Trading, Wave Computing, and Zomojo.
How can I contact Yi-Chen(John) Li?
You can use AeroLeads to view verified contact signals for Yi-Chen(John) Li at BlackEdge Capital, including work email, phone, and LinkedIn data when available.
What schools did Yi-Chen(John) Li attend?
Yi-Chen(John) Li holds Electrical Engineering, Electronic & Computer Engineering from University Of Sydney.
What skills is Yi-Chen(John) Li known for?
Yi-Chen(John) Li is listed with skills including Fpga, Asic, Digital Signal Processors, Systemverilog, Verilog, Vlsi, Semiconductors, and Embedded Systems.
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