Jonathan L. Email & Phone Number

My Server Tools: mcelog, dmidecode, lspci, setpci, i2cdetect, i2cset, i2cget, ipmitool [raw, sdr, sel, sensor], yafuflash, socflash, smartctl, nvme, hexdump, DIMM SPD, ECC, etc.Managing OEM/ODM/JDM x86 server platforms:* Platform: Tyan S7106, S7126. Intel S2600WF Wolf Pass.* CPU: Intel Xeon Sapphire Rapids, Icelake, Cascade Lake, Skylake, Ivy Bridge & Sandy Bridge. AMD Opteron. * Chipset: Intel Purley Lewisburg C62X; Patsburg C60x. AMD SR5650/SR5690/SP5100. * BMC: Aspeed AST2500, AST2300, AST2150.* LAN: Intel 82574, i210-IS and i350-AM4. * HBA: Broadcom LSI SAS9380, SAS2308, SAS2008. Expander: SAS35x36, SAS2x20.* FW: AMI BIOS and BMC.2010 to 2015: Completed full product development lifecycle of Riverbed’s Gen 6 (Redfin) platform.* ODM platform based on AMD Opteron 41xx/42xx CPU family.* Initial concept in 2010, mid-cycle product refresh in 2012, and end-of-life in 2015. * With 60+ SKUs across 1U-3.5, 2U-3.5 & 2U-2.5 platforms.2015-2019: Completed full product development lifecycle of Riverbed’s dual-node (Bluefin) platform.* JDM custom dual-node platform based on Intel Ivy Bridge-EP (E5-26xx v2) CPU family.* Motherboard with 2 nodes: Host and Hypervisor.* Host node provides Riverbed’s RiOS WAN optimization. * Hypervisor node for bare-metal virtualization in ESXi 6.0.* More info: https://support.riverbed.com/bin/support/static/8la2e9l7m8tdffaa302dmf3mpp/html/dsr8arkt495s09dq5ec1ficqcu/sf_edge_5.5_icg_html/index.html#page/sf_edge_5.5_icg_html/overview.3.4.html2018-Present: Currently working on Riverbed's Gen 8 (Marlin) platform.* Motherboard based on Intel Xeon Skylake & Cascade Lake CPU family.* GA’d in Q1’2019. * Managing hardware EOLs, firmware bugs and updates.* Completed 2nd round of regulatory compliance.* More info: https://support.riverbed.com/bin/support/static/if1iqqnj1cielmj1gkpn1mkf45/html/885cf9jham3615a9t5qc64h6um/sh_cx_9.9_icg_html/index.html#page/sh_cx_9.9_icg_html/app_spec_xx80.html

Venture funded startup specializing in patented capacitive sensors and networks.Managed an R&D team consisting of HW, FW, SW, and ME.Delivered world’s first capacitive load cell (weigh scale) with USB connectivity.Won “Product Innovation of the Year” award from Frost & Sullivan in 2007.Participated in raising $12M venture financing.Revamped entire product line which generated first $1M revenue.

I took care of an 18-slot Backplane and a 60Gbps Fabric Switching Card. I put the SONET card on a diet to remove 30% COGS.In my "gap" time, I designed a 96-port POTS card and a 48-port UVG card. I fixed CMOS latchup, designed NEDS/SBC compliant hotswap and resolved power-sequencing issues.In my "recreation" time, I arm-wrestled Zeus to get LFR and LCAS to survive lightning strikes.

VINA's founding R&D team. I was the sole hardware designer for the first year. I did VINA's original IAD platform including FXS, FXO, and DSP cards.I managed a hardware team to design a C.O. chassis with GR-303 concentration and frame-relay aggregation, at the edge of the access network.