Jon Herr Email & Phone Number

Rio Rancho, Nm, Us

East Aurora, New York, Us

Albuquerque, Nm, Us

DO-254 validation of Fiber Optic Video (ARINC 818) video converters. The converters allow for interfacing between ARINC 818 and DVI in flyable applications.

Charlotte, Nc, Us

Senior FPGA design engineer for flyable application.* Performed upgrade of actuator controller FPGA design to consolidate three (3) FPGAs in to one FPGA. * Designed motor controller FPGA resolver interface.* Designed multiple sensor interfaces during the upgrade to change position sensor from linear potentiometer to LVDT. * Designed new telemetry / data collection module to collect new sensor data and provide scheduled data to servo control algorithm.* Designed new in system debug for profiling servo / actuator control loop tuning.* FPGA design required different roles on different installations within overall system. Designed in personality location pins to alter telemetry collection changes, behavioral changes, based on installed board within system. One FPGA for all simplified logistics and installation during system test. * Performed all design (Verilog / VHDL) and verification to deliver a first pass success deliver on target platform.

Us

* Performed design / verification on multiple ASICs for a variety of applications. * Designed an 8 bit microcontroller utilizing a microcoded architecture for an automotive application.* Designed a 82527 CAN protocol controller clone for multiple industrial applications.* Worked on a large team to design a 32 bit microcontroller with deterministic execution features and flexible I/O. Deterministic features required novel context aware register sets and peripherals.* Developed new prototyping method using large FPGAs to emulate ASIC I/O structures and voltage level conversions. Voltage level conversion design from low level FPGA I/O voltage to target system I/O provided a configurable active drive on each I/O line as required for target system. * Designed multiple ASIC emulations for FPGA fabric including the adaptation of asynchronous RAM to synchronous structures, glitch swallowing logic, etc. * Performed RTL language migration from obsolete languages such as Altera AHDL to Verilog in order to migrate designs or assist customer integration / debug.