Jon Stephan Email & Phone Number

Boston, Ma Area

Hudson, Ma

Developed Xeon processor soft error rate modeling capabilities, including system-level statistical fault injection for program vulnerability factor calculations. Developed new hardware soft error rate testing methodologies. Continued to own product soft error rate proton and neutron beam testing.

Intel Development Group, Hudson, Ma

Owns assessing product SER performance through beam testing, and driving the development of capabilities related to product SER testing and modeling, and to providing technical guidance to Intel on managing SER performance for future products. Coordinates all aspects of system level beam testing for Xeon, Xeon Phi, Itanium and Atom products, including hardware and workload set up, beam testing logistics and data analysis.

Enterprise Microprocessor Group

Product Quality and Reliability Engineer for the Itanium processor family. Primarily focused on frequency degradation guardband bin split optimization and Vccmin erratic bit analysis. Set up the lab and ran the Itanium system stress experiments. Set up the Itanium on-site validation (OSV) system and wrote the test flow controller software. Chaired the CPU-Chipset Goals And Use Conditions Joint Engineering team.

Chipset Product Division, Folsom, Ca

Technical lead for Chipset Design in Quality and Reliability team, responsible for analysis of electromigration, gate oxide breakdown, vccmin erratic bit, frequency degradation and soft error rate. Designed a novel “NAND-fill” test chip to measure metal layer defect density.

Flash Memory Product Division - Folsom, Ca