Senior software manager for development of new system characterization tooling.

Managed 2 agile teams of software developers and QA engineers.• Stepped-in to manage a new open-source project aimed to provide a standard library interface for Intel GPU performance metrics. Brought project from a POC to initial product and delivered first 4 binary releases, inclusion as a new component in Intel oneAPI, and upstream to PyTorch Profiler.• Managed a diverse team of expert developers, established processes, and represented the project to management and release partners while simultaneously continuing to manage SoCWatch.• Managed development and test team and made direct code contributions for primary system telemetry tool used widely by Intel and OxM/OS customers for power management measurement and debug.• Ran Agile planning processes as product owner and first-line people manager, collected requirements from stakeholders and customers, maintained devops systems, and managed hardware lab environments.• Effectively planned and executed project operations through extensive use of Jira for issue tracking/planning and GitHub/GitHub Actions for code development and continuous integration.

Developed software for embedded platform power and performance monitoring tools based on C++ and Java (Eclipse). Managed a device lab supporting power monitoring tool development and testing across PC Client, Mobile, and a variety of Embedded product segments.

Developed software for embedded platform power and performance monitoring tools based on C++ and Java (Eclipse).• Developed a Node.js-based JavaScript/HTML5 cross-platform real-time power data collection and visualization tool that optimized real-time performance of an associated time-series data display UI.• Executed various code re-factorings and software lifecycle process steps to prepare the tool for suite integration and eventual external product release.• Developed and maintained a Java-based Android application for real-time capture and display of various system metrics for analysis of performance, power, thermals and more.

Managed a small team responsible for behavioral performance modeling of CPU and GPU implementations, generating benchmark-level performance projections, and validating actual microprocessor performance pre- and post-Silicon.• Re-aligned development efforts around a new high-level graphics simulator which addressed many limitations of the existing graphics simulation capabilities.• Integrated iGPU performance simulator with an existing CPU cache and memory model, enabling much faster turn-around time, broader set of workloads, and the ability to connect both flavors of Intel’s iGPU cores to the shared on-die cache.• Directed team’s efforts to improve the model’s accuracy and execute a variety of cache and memory bandwidth studies, which led to decision to add a Mid-Level Cache into future iGPU designs.• Correlated simulator to existing silicon in order to improve accuracy and confidence in projections.• Directed 2 rounds of exploratory R&D with inputs from multiple internal teams, culminating in successful approval of 7 new Uncore features to 2011 CPU product that improved multi-threaded performance.• Acted as an individual contributor for final 6 months before transferring to the software organization. During this time, successfully modeled a novel replacement policy for front-end micro-operation cache that significantly simplified implementation while improving performance. Feature was ultimately implemented in 2015 CPU product.

• Integrated Graphics Exploration: Transitioned successfully from CPU into GPU knowledge domains with no prior experience in graphics. Played a key role in Intel’s strategic decision to integrate the GPU into the CPU die in the forthcoming 2010/11 product by becoming the first person in the company to add a large Last Level Cache model to a graphics simulator and use it to quantify significant performance gains to be had by moving the GPU on-die with the CPU behind a shared cache.• Performance Simulator Developer: Modeled specific blocks of the CPU micro-architecture in high-level, cycle-accurate simulators based primarily in C/C++/SystemC. Acquired a deep and broad knowledge of the Fetch/Decode frontend, Caching Hierarchy, and Memory Interfaces across 3 CPU design cycles in P4, Core-2, and Core-I series integrated graphics designs.• Performance Projections: Produced quarterly estimates of projected CPU performance throughout the design cycle, accomplished using direct simulation of the projected design running representative subsets of key industry-standard CPU benchmark workloads combined with analytical projection models.• Performance Validation: Pre-Silicon - Validated the correctness of the CPU’s RTL implementation by correlating it to a cycle-accurate performance simulator. Root-caused and fixed any discrepancies in either RTL or simulator, improving confidence in RTL to match simulator projections. Post-Silicon - Measured benchmarks on first chips in actual systems, verifying results against pre-Silicon projections. Debugged and tuned hardware and firmware settings for optimal performance prior to shipping product.

Validated board-level HDL and schematic designs through hardware/software co-simulation tools for emerging optical-networking platform. Wrote Perl scripts to automate tasks and published results.

Performed electromechanical R&D work on future high-field magnets for particle accelerators such as the Large Hadron Collider (LHC).• Responsible for Finite Element-based physics simulations using ANSYS, 3D CAD design for prototype fabrication, and co-authoring of design study reports with a lead physicist.

Performed electromechanical R&D work on future high-field magnets for particle accelerators such as the Large Hadron Collider (LHC).• Responsible for Finite Element-based physics simulations using ANSYS, 3D CAD design for prototype fabrication, and co-authoring of design study reports with a lead physicist.