Overall Architect, Back-end Developer, and Team Leader- Drive and oversee all architectural changes to the global Edge Cloud micro services platform to ensure stability, scalability, security, privacy, and functionality.- Write code for advanced edge deployment features in the back-end micro services, including distributed data management, automated Docker and Kubernetes deployments, developing REST APIs and data structures.- Ensure excellent code quality by establishing coding, code review, and unit and e2e test practices. Review all back-end services code by other engineers and offer constructive feedback.- Provide growth opportunities for other engineers by encouraging entire team participation in architecture, code, and design review discussions.

• Excellence in Technical Leadership, System Architecture, and Software Development• Design and implement Network Virtualization functions that tie together software services with hardware switch chip acceleration to slice the network• Design and implement Distributed Systems for configuration synchronization (4-phase master-less protocol) in a multi-node fabric, and state synchronization in a 2-node cluster for redundancy and sub-second failover• Imagine new tools and features for enhanced transparency and debug-ability like flowtrace that shows live packet paths through a multi-node fabric with redundant paths• Advise and guide the development of new software features and architectures• Review peer work and hold development to a high standard

Research and development of high speed asynchronous circuits for next generation computingResearch and development of capacitively coupled chip-to-chip communication technology for high bandwidth I/O on stacked chips- full custom analog circuit design and simulation in Spice, Verilog- schematic capture and layout in TSMC 180nm, 90nm, 40nm technologies- taped out multiple test chips and verified high speed asynchronous circuits working as expectedCAD tool development- in-house CAD tool development in both C and Java for schematic, layout, simulation- implemented Logical Effect analog circuit sizing algorithm for optimal transistor sizes