Jonathan Sippel Email & Phone Number

Jonathan Sippel is a Physical Design Engineer at Intel Corporation at Intel Corporation. He possess expertise in physical design, timing closure, primetime, asic, tcl and 18 more skills.

Listed skills include Physical Design, Timing Closure, Primetime, Asic, and 19 others.

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  Physical Design Engineer

  Intel Corporation

  May 2004 - Present

  • Developed timing environment, methodologies and timing constraints necessary for physical synthesis of 90nm/45nm media ASIC.• Defined/validated/implemented timing ECOs.• Performed timing/DRC correlation experiments across various tools (PrimeTime, ICC, Star) to establish timing configuration settings and/or define methodology uncertainites.• Designed clock tree/clock tree specs to minimize timing closure loops during tape-in.• Worked with board-level design engineers to develop t-spec AC timings• Performed schematic entry for designs and verified functional connections through formal verification• Placed, routed, and re-floorplanned several designs to facilitate timing/DRC closure• Have independently and co-written several TCL scripts to automate our design flows with improved efficiency.• Experience with following tools: (Synopsys) Primetime, DesignCompiler, PhysicalCompiler, Astro, IC Compiler, StarRCXT; (CADENCE) Virtuoso, Ostrich, First Encounter

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  Rochester Institute Of Technology

  Electrical Engineering; Science