Jonathan Sprague Email & Phone Number

Round Rock, Texas, US

• Platform Architect for the Telecom Systems Business's Infrastructure Engineering team defining next generation RAN and Edge platforms for the Telecom industry
• Directly engaged with end customers and account teams to enable successful RAN deployments as well as providing engineering support for critical issues

Round Rock, Texas, US

Round Rock, Texas, US

North Reading, MA, US

• In charge of the Hardware PCB team that develops all the test site electronics hardware for the Teradyne System Test organization
• Management duties include oversight of full time Teradyne hardware engineering staff (US and Philippines) as well as contract engineers and sub-contractor design houses
• Actively staffing up local and remote teams in preparation for new product design cycles

Round Rock, Texas, US

• Responsible for defining future platform hardware architectures in Dell EMC's Isilon Scale-Out NAS solutions
• Continuously collaborating with Product Management to refine internal and market requirements into planned future roadmap product offerings
• Leading cross-functional technical collaboration with Platform and Systems Engineering, Global Supply Chain and other internal teams to define new hardware designs for future storage platforms
• Actively engaged with members of the Office of the CTO in analyzing future looking technologies in the CPU, memory and storage spaces

Round Rock, Texas, US

• Systems Engineering Lead responsible for gathering requirements for the next generation Enterprise class compute and storage platforms
• Actively analyzing forward looking technologies in the CPU, Storage Class Memory, and Fabric spaces with a focus on next generation Enterprise Storage use cases

Round Rock, Texas, US

• Hardware Engineering Lead on an innovative, composable, Converged Infrastructure appliance proof of concept. Developed the key hardware and internal fabric architecture for the program. Responsible for overseeing the.
• Working manager overseeing a small team of Senior and Principal engineers as well as college co-op students. Managed status updates and feedback on professional growth via 1:1 meetings as well as performance.
• Hardware Engineering Lead on the Data Domain DD9800 hardware platform. Oversaw a JDM design team (Inventec) comprised of logic, SI, firmware, mechanical and thermal engineers. Managed internal and external PCB design.
• Created initial high-level hardware architecture for VMAX all flash kicker project that was productized as the VMAX 250F and 950F. Worked to minimize design risk by basing the bulk of the design on the existing.

Round Rock, Texas, US

• Hardware Engineering Lead that successfully launched a common hardware platform used in the following storage products: VMAX3 Family (100K, 200K, 400K), VMAX All Flash Family (450F, 850F), VNX (VNX8000), and Data.
• Led small critical response teams that performed root cause analysis on high profile issues including DIMM soft errors, CPU IERRs, ESD testing failures and transportation board flex failures. Reported failure analysis.
• Board Lead on a dual socket Intel Sandy Bridge/Ivy Bridge motherboard design. In charge of all aspects of the design including specification creation, schematic capture, constraint entry, and layout support. Worked to.
• Board Lead on an I/O Annex that extended I/O support to two additional I/O Modules for the VMAX V2 product line.
• Point person in charge of all testing and documentation related to thermal throttling on FBDIMMs used in the first Intel based VMAX solution. Analysis used to create closed-loop throttling algorithm in BIOS

Round Rock, Texas, US

• Junior motherboard designer on converged hardware platform used by Symmetrix (VMAX) and Clariion (CX4-960). In charge of the Intel southbridge and management Ethernet areas of the design.
• Led documentation of a cross-business unit SMI Error Handler document that provided the framework for all PCIe, protocol and internal errors across multiple product lines
• Led SMI handler fault injection effort using Agilent PCIe exercisers.

Round Rock, Texas, US

• Designed a 2G/4G Fibre Channel/RS-232 diplexing debug card for the purpose of separating an RS-232 diplexed signal from a Fibre Channel signal in EMC systems
• Performed EVT/DVT testing and debug as well as SPOF (Single Point of Failure) testing on the latest storage platforms currently in development for the EMC2 midrange group
• Verified that current I/O modules on said platforms met industry standards for 100TX and 1000TX Ethernet compliance
• In charge of PCI Express Compliance testing for NSX/CX3-80 project
• Performed software testing and debug on EMC Celerra and CLARiiON NS700 systems
• In charge of multi-vendor mix eight corner environmental testing

• Worked as a hardware designer in both the hardware and production departments
• Created the schematics for a 5 mega-pixel video adapter that went into production
• In charge of assembling a digital flat panel medical workstation prototype and preparing it for display at RSNA 2001
• Worked extensively in quality control monitoring defects in 3 megapixel and 5 megapixel LCD glass from the supplying manufacturers (IBM and LG)
• Discovered and recorded a previously unknown defect in the 3 megapixel glass
• Worked in the production lab debugging and reworking all types of video boards in use by our customers