Senior Ip Design Engineer - Pixel Ip
CurrentRTL Design & Integration, plus front-end design/synthesis, firmware/driver support of various IPs. Faking it until I can make it.
Apr 2014 - Present
AeroLeads people directory · profile
Jonathan Choy Email & Phone Number
Senior IP Design Engineer - Pixel IP
at
Apple
1 work email found
@apple.com
8 phones found area 408
LinkedIn matched
✓ Verified August 2026
4 data sources
Profile completeness 100%
Current company
Role
Senior IP Design Engineer - Pixel IP
Location
San Francisco Bay Area, United States
Who is Jonathan Choy? Overview
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Quick answer
Jonathan Choy is listed as Senior IP Design Engineer - Pixel IP at Apple, based in San Francisco Bay Area, United States. AeroLeads shows a work email signal at apple.com, phone signal with area code 408, and a matched LinkedIn profile for Jonathan Choy.
Jonathan Choy previously worked as ASIC Design Engineer - CPU Implementation/PD at Apple and Sr Design Engineer at Advanced Micro Devices. Jonathan Choy holds Master Of Science (Ms), Electrical Engineering from University Of California, Berkeley.
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Email format at Apple
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{first_initial}{last}@apple.com
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AeroLeads found 1 current-domain work email signal for Jonathan Choy. Compare company email patterns before reaching out.
Profile bio
About Jonathan Choy
Currently doing front-end RTL design, integration, & driver support of power-efficient non-microprocessor IPs for custom Systems-on-Chip (SoC).Previously: 10.5 yrs experience in logic/physical design & implementation of low-power/high-performance microprocessor circuits. Mildly involved in design flow development/special-interest groups as well. Prior to that, two summers & one semester's worth of experience as an intern in back-end CAD development (DRC/LVS rules, custom scripting for Mentor tools, providing support to designers/consumers-of-the-tools).Specialties relevant to work experience: logic design & debug, timing closure, electrical verification, implementation/physical design (PD), and of course, being a code-monkey as needed to help me with my work. Also some experience/familiarity with multi-domain power-intent design/builds/verification in the push for ever-lower power consumption.Buzzwords: verilog, perl, tcl, unix, linux, shell scripting, mentor, cadence, synopsys, rtl compiler, design compiler, spyglass, dcg, ic compiler, low power, encounter, cdc, formality, conformal, lec, eco, conformal-lp, mvrc, cpf, upf, cts, lvs, erc, drc, html, rtfm.
Listed skills include Ic, Microprocessors, Timing Closure, Logic Design, and 12 others.
Current workplace
Jonathan Choy's current company
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4 roles
Jonathan Choy work experience
A career timeline built from the work history available for this profile.
Asic Design Engineer - Cpu Implementation/Pd
CPU design as part of Silicon Engineering Group (formerly Mobile Silicon design team). Logic-level/physical implementation of various parts of microprocessor circuits (mapper, scheduler, execution unit, memory/bus interface unit, cache interface, among others), at individual block-level, and some responsibility for top-level verification/low-power analysis flows (buzzwords listed elsewhere).Involved in some high-level design/feasibility studies in early project-definition phases, and also went along for the ride in the industry-wide shift from custom-design/implemented circuits to pure-physical-design-let-the-tools-do-all-the-thinking flows, which greatly enhanced my tcl scripting, code-monkeying, and tool-using abilities.If I was able to pick up IC Compiler in three weeks, I figure I can do anything.
Dec 2008 - Mar 2014
Sr Design Engineer
logic-level design & phys. implementation of microprocessor circuits. most recently involved in architectural & logical design of Bulldozer floating point unit. previously involved in implementation of DDR2-Northbridge on K8. Role was very vertical, involving all aspects of flow from RTL/architecture development to backend physical design tapeout.
Sep 2003 - Dec 2008
Cad Co-Op/Intern Engineer
Support CAD tools for back-end of design flow (DRC/LVS rule deck maintenance, in-house Mentor script maintenance, etc.)Convinced me that I did not want to pursue a career in CAD, and gave me a new respect for the guys who actually are in CAD.
May 2000 - Aug 2001
2 education records
Jonathan Choy education
Master Of Science (Ms), Electrical Engineering
University Of California, Berkeley
Bachelor Of Science (Bs), Electrical Engineering And Computer Sciences
University Of California, Berkeley
FAQ
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What company does Jonathan Choy work for?
Jonathan Choy works for Apple.
What is Jonathan Choy's role at Apple?
Jonathan Choy is listed as Senior IP Design Engineer - Pixel IP at Apple.
What is Jonathan Choy's email address?
AeroLeads has found 1 work email signal at @apple.com for Jonathan Choy at Apple.
What is Jonathan Choy's phone number?
AeroLeads has found 8 phone signal(s) with area code 408 for Jonathan Choy at Apple.
Where is Jonathan Choy based?
Jonathan Choy is based in San Francisco Bay Area, United States while working with Apple.
What companies has Jonathan Choy worked for?
Jonathan Choy has worked for Apple and Advanced Micro Devices.
How can I contact Jonathan Choy?
You can use AeroLeads to view verified contact signals for Jonathan Choy at Apple, including work email, phone, and LinkedIn data when available.
What schools did Jonathan Choy attend?
Jonathan Choy holds Master Of Science (Ms), Electrical Engineering from University Of California, Berkeley.
What skills is Jonathan Choy known for?
Jonathan Choy is listed with skills including Ic, Microprocessors, Timing Closure, Logic Design, Silicon, Asic, Soc, and Verilog.
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