Jonathan Burrows Email & Phone Number

San Francisco, CA, US

Oakland, California, US

Oakland, California, US

• Lead development of company policy and author internal position papers and external regulatory filings for various initiatives relating to energy efficiency, including cost effectiveness policy, energy goals and.
• Represent PG&E EE policy on internal cross-functional teams and in external statewide and national industry and regulatory forums.

Oakland, California, US

• Managed PG&E's award-winning Supply Side and Excess Supply demand response (DR) pilots, which pioneered integration of demand response and distributed energy resources into the California wholesale energy markets as.
• Actively supported the distributed energy resource (DER), energy storage, and self-generation proceedings at the CPUC and CAISO as a subject matter expert and by contributing language to various PG&E filings in these.
• Managed PG&E’s Demand Response Emerging Technologies (DRET) program and was tasked with identifying and testing technologies that can enable or enhance customer demand response capabilities and then transferring.
• Managed PG&E’s Permanent Load Shifting (PLS) program - Responsible for all aspects of program design/development, implementation, oversight, and vendor management. - Primary author for CPUC application and other.

San Francisco, CA, US

• Reviewed more than 15 power purchase agreements (PPAs) submitted by California utilities for procurement of large-scale renewable energy from a variety of in-state and out-of-state renewable technologies, including.
• Authored multiple California Public Utilities Commission (CPUC) resolutions approved by the Commission.
• Provided market and technical analysis on a variety of topics (including renewable energy solicitations, utility solar PV programs, tradable renewable energy credit (TREC) caps, and energy market size) used by.
• Participated in contract review and PRG meetings for the three large California Investor Owned Utilities.

• Consultant in the areas of semiconductors and photovoltaics (PV) with Gerson Lehrman Group Councils (GLG Educator), Reuters Insight Expert Network, Vantage Marketplace, and Guidepoint Global Advisors.
• Mentor for 2009, 2010, and 2011 Clean Tech Open.

Santa Clara, California, US

• Managed deployment and application of PDF infrastructure and methodologies needed to support use of PDF test chips on engagement projects.
• Identified and continually collected key deployment and application metrics, and used metrics results to drive internal process development and improvements.
• Worked with internal yield analysis software development group to spec new software features and bug fixes.
• Supervised, trained, and career managed a team of applications engineers.
• Worked with capital equipment vendors on joint development of inspection and failure analysis methodologies.
• Developed and managed defect inspection and failure analysis BKM’s and application methodologies for use on all consulting projects.

Santa Clara, California, US

• Team member on three person consulting team working with major European IC manufacturer to identify and solve performance and yield problems for client’s CMOS image sensor process over multiple fabs.
• Responsibilities included working with client on identification and diagnosis of product/process yield loss mechanisms and creating a yield improvement plan for long-term manufacturing improvement as well as immediate.
• Continuous interaction with client at both engineering and management levels, including over 50% direct onsite client interaction and support.

Santa Clara, California, US

• Managed test chip design projects for leading-edge semiconductor technology development.
• Supervised, trained, and career managed a team of test chip engineers.
• Worked with sales and marketing groups to sell engagements and write engagement contracts and SOW’s.
• Developed project cost models and resource plans for all design projects.
• Scheduled and assigned design group resources (over 15 engineers).
• Identified and continually collected key design through mask manufacturing process metrics, and used metrics results to drive internal process development and improvements.

Santa Clara, California, US

• Determined manufacturing process issues by working directly with clients, which included some of the world’s largest foundry, fables, and IDM semiconductor companies.
• Designed test chips to diagnose causes of process problems.
• Supervised and trained other engineers.
• Developed software specifications for various internal software tools used in design and verification process.
• Worked on leading-edge semiconductor technology development.

Santa Clara, California, US

• Oversaw photolithography mask manufacturing and defect inspection for the two most critical IC layers.
• Developed several tools and procedures to improve quality and cost efficiency of manufacturing process.
• Qualified second source vendors of Intel technology.
• Worked on leading-edge semiconductor technology development.
• “Owned” production tool.
• Supported production by addressing and troubleshooting problems encountered in the production line.

Pasadena, CA, US

Developed and tested various unique materials for use in consumer, industrial, and military products.

Livermore, CA, US

Developed new manufacturing methods to decrease production time of FormFactor’s products.