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Jonathan Ou Email & Phone Number

Server SoC Performance at AMD
Location: Austin, Texas, United States 5 work roles 2 schools
1 work email found @amd.com LinkedIn matched
✓ Verified Jul 2026 4 data sources Profile completeness 100%

Contact Signals · 1 work email

Work email j****@amd.com
LinkedIn Profile matched
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Current company
AMD
Role
Server SoC Performance
Location
Austin, Texas, United States

Who is Jonathan Ou? Overview

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Quick answer

Jonathan Ou is listed as Server SoC Performance at AMD, based in Austin, Texas, United States. AeroLeads shows a work email signal at amd.com and a matched LinkedIn profile for Jonathan Ou.

Jonathan Ou previously worked as CPU Performance Architect at Intel Corporation and IP Logic Design Engineer at Intel Corporation. Jonathan Ou holds Masters, Computer Science (Machine Learning) from Georgia Institute Of Technology.

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Email format at AMD

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{first}.{last}@amd.com
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AeroLeads found 1 current-domain work email signal for Jonathan Ou. Compare company email patterns before reaching out.

Profile bio

About Jonathan Ou

Electrical Engineer with focus in CPU Performance Modeling, RTL, Micro-Architecture, and Physical Integration. Experience with CPU/IP Blocks/SOC System with focus on High Performance and Low Power Design. Design data tracking and analysis to improve project efficiency (Timing and Power). Interests in Machine Learning and Data Analysis

Listed skills include Verilog, Computer Architecture, Functional Verification, C, and 20 others.

Current workplace

Jonathan Ou's current company

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AMD
Amd
Server SoC Performance
Sunnyvale, California
Website
AeroLeads page
5 roles

Jonathan Ou work experience

A career timeline built from the work history available for this profile.

Server Soc Performance

Current
Amd

Santa Clara, California, Us

Mar 2022 - Present

Cpu Performance Architect

Santa Clara, California, Us

Microarchitecture performance simulator developmentPer-silicon performance analysisSimulator and design correlation analysis

Jan 2017 - Mar 2022

Ip Logic Design Engineer

Santa Clara, California, Us

RTL Design - Worked on projects with RTL level design/implementation as main duty. Involved with Specification, Micro-Architecture, RTL Design/Test, and Back End phases to achieve High Performance and Low Power. Including mapping, partitioning, I/O specification, and data/control path considerations.Integration - Worked with DC and ICC to find Back End solutions to various design challenges (Timing/Power/Congestion/etc). Understanding of Back End design methodologies/stages to achieve High Performance Synthesis/Placement/Route with Low PowerLow Power - Led cluster team in power convergence. Participated in early power estimation/budget along with power optimizations and considerations at different stage of design. Wrote scripts to generate and analyze data for different workloads targeting various performance metrics to find high ROI power savings opportunities (Micro-Architecture, RTL, and Backend). Timing Convergence - Led cluster team in timing convergence. Involved with early design block level placement, RTL timing optimization, and Back End timing optimization. Analyzed and tracked critical timing issues of design in various stages (WNS and TNS).ECO work – Involved with A0/B0 stepping completions. Wrote automated scripts to fix physical design violations such as slope, cap, and max/min timing. Data analysis on design to find impact of cell degradations to automate fixes with minimal DRC cleanup. Wrote scripts to automate scan chain re-stitching in eco flow with minimal disturbance.

Jun 2011 - Jan 2017

Intern

Santa Clara, California, Us

- Involved in the back end and front end design process of the Atom processor - Worked on firewall interface subunit between the core and bus- Worked on different methods to shrink area and power

Jan 2010 - Jun 2011

Interim Engineering Intern

San Diego, Ca, Us

- Involved in the functional Verification of Qualcomm’s Latest QDSP6 processor core- Created and managed sub-unit test bench for the ALU- Implemented Assertion based verification for entire core with input from other Design Engineers

May 2009 - Dec 2009
Team & coworkers

Colleagues at AMD

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2 education records

Jonathan Ou education

Masters, Computer Science (Machine Learning)

Georgia Institute Of Technology

Bachelor Of Science, Electrical Engineering

The University Of Texas At Austin
FAQ

Frequently asked questions about Jonathan Ou

Quick answers generated from the profile data available on this page.

What company does Jonathan Ou work for?

Jonathan Ou works for AMD.

What is Jonathan Ou's role at AMD?

Jonathan Ou is listed as Server SoC Performance at AMD.

What is Jonathan Ou's email address?

AeroLeads has found 1 work email signal at @amd.com for Jonathan Ou at AMD.

Where is Jonathan Ou based?

Jonathan Ou is based in Austin, Texas, United States while working with AMD.

What companies has Jonathan Ou worked for?

Jonathan Ou has worked for Amd, Intel Corporation, and Qualcomm.

Who are Jonathan Ou's colleagues at AMD?

Jonathan Ou's colleagues at AMD include Matthew Beasley, Howard Pan, Sateesh P, Ching Weng-Yin, and Marijke Vandepitte.

How can I contact Jonathan Ou?

You can use AeroLeads to view verified contact signals for Jonathan Ou at AMD, including work email, phone, and LinkedIn data when available.

What schools did Jonathan Ou attend?

Jonathan Ou holds Masters, Computer Science (Machine Learning) from Georgia Institute Of Technology.

What skills is Jonathan Ou known for?

Jonathan Ou is listed with skills including Verilog, Computer Architecture, Functional Verification, C, Vhdl, Perl, Rtl Design, and System Verilog.

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