Jonathan Thurgood Email & Phone Number

• Inventing
• HARDWARE DESCRIPTION LANGUAGE (HDL) INCORPORATING STATISTICALLY DERIVED EXPERIMENTAL DATA AND RELATED METHODS (VerilogA/DoE) - Provisional Patent Application Serial No. 60/582,178 Converting to full patent in June.
• Designed and implemented Timer/Counter/PWM, Clock Distribution, AHB interface all for Cypress’ PSoC.
• Worked on sub blocks and have a good understanding of full system level operations of Cypress’ True Touch chips.
• Architected and implemented DFT strategy for PSoC’s Universal Digital Block—including methodology, implementation and scripting to execute manufacturing vectors out of a small 512 byte cache.Teaching
• Created and taught a Cypress University Course (B4) to instruct Cypress employees, worldwide, in the usage of the before mentioned patent (VerilogA/DoE)

• Designed and implemented, in synthesizable RTL, a USB core and test benches. Wrote micro-code, prototyped it into a Xilinx FPGA, certified the design with the USB IF. Wrote a hardware driver to test the USB core on a PC.

Assisted a Senior Scientist implement experiments.Developed post experiment analysis software.