Custom Ic Methodology Solutions Director – Physical Design
CurrentManagement responsibilities for the CIC Methodology Implementation Group Physical Design team. Custom/Analog IC physical design enablement for enterprise customers at FinFET (7,5,3nm) technologies. Drive EDA tool enhancements, develop custom solutions and deliver targeted training to improve FinFET custom/analog physical design efficiency. Development and delivery of Cadence internal advanced node physical design training for the worldwide AE community. Shared responsibilities for managing, developing, and testing advanced node custom design reference flows. Expertise in FinFET EDA tools and methodology. FinFET custom/analog physical design expert including mixed signal interoperability. Services AE of the Year 2020. Creator of the original Methodology Enablement Package (MEP); a set of components to enable efficient assisted and automated device level custom layout functionality.
