As the section head for the communications security (COMSEC) section for the Naval Research Laboratory I am responsible for the management of a budget of over $10,000,000 per year distributed over multiple programs. The programs that I manage cover the full scope of communications security ranging from cross domain solutions (CDS), cryptographic modules, end cryptographic units (ECU) and key management systems. Currently developing next generation End Cryptographic Units (ECU) which are fully compliant with National Security Agency (NSA) Cryptographic Modernization version 2 (CM2) requirements. The ECU's implement both NIST and NSA Post Quantum Cryptographic (PCQ) algorithms.I have a team of over 20 scientists, engineers and contractors. My team is experienced in both NSA Type-I crypo certification and NSA CDSMO CDS certifications. My team handles the full cycle of product development from initial concept to certification and deployment.

Served in multiple roles on multiple projects ranging from Type 1 (NSA certified) embedded cryptographic modules to network connected cryptographic modules.As technical lead for projects developed policies and procedures such that the software, hardware and firmware teams are capable of being certified as a CMMI level three organization. Improved communication across teams by developing procedures to incorporate the use of collaborative software (Wiki pages, document repository etc.) into day to day activities. Worked with subcontractors by developing requirements documents, soliciting bids, selecting bids and tracking progress. Managed the day to day activities of the interdisciplinary (software, hardware, firmware) development team.As a systems engineer worked with sponsors to define and refine the requirements of systems under development. Developed process for the management of requirements in requirements management software (Polarion). Developed executable models of systems in Rational Rhapsody utilizing SysML. Participated in and lead system re-architecture discussions (new processor selection, transition from 16-bit parallel bus to high speed PCI Express [PCIe]).As Software lead gathered software specific requirements for systems under development. Managed the day to day activities of a team of three software engineers. Mentored less senior engineers.

As a member of the software team developed software and participated in certification testing for the Programmable Embeddable INFOSEC Product (PEIP) Phase II. Tasks included but was not limited to, designed and implemented HDLC based protocol for communication between the cryptographic core and host boards. Implemented DS-101 protocol for communication to benign fill devices such as a Data Transfer Device (DTD). Designed and implemented software for a host card capable of exercising the PEIP via automated scripting. Designed and implemented software for a (Ethernet) network capable host card.

As a senior member of the software team developed design documentation, user documentation and software for the PRIU portion of the FAA NEXCOM project. Solely developed software and supporting documentation for a system capable of digitizing voice, provide audio rate conversion and interfacing to an ATC-10B voice encoder. Took responsibility for the software and documentation for the Voice Encoder Module (VCM) portion of a radio interface unit (RIU). Developed protocol used for intermodule communication in a chassis.

As a member of the firmware team developed embedded software for telephony edge switches based on the Motorola Power PC processor (603, 7xx). The firmware was developed in a mixture of C and Power PC assembly. Tasks included but not limited to, X-Modem upload, download utility, BIOS flash update utility, driver for TI 1410a PC-Card controller, driver for compact flash based memory modules, driver for IBM Micro-drive, driver and diagnostics for AMD Ethernet controllers, driver for Motorola MPC107 memory and PCI controller, initial board bring up. As general firmware lead for two projects was required to develop schedules, requirements document and user documentation.

Optimized image compression and manipulation algorithms by rewriting in assembly to take advantage of MMX and XMM SIMD instructions available on Intel Pentium II and Pentium III processors. Designed and implemented algorithm to convert 30 f.p.s. Video to 24 f.p.s. (3:2 push up). In a mixture of C and C++ developed a simple video processing utility capable of manipulating digitized video in a variety of raw (uncompressed) formats (YUV16, RGB32, RGB24, etc). The utility was able to perform gamma correction, crop, filter, 3:2 push up, display and convert to other digital video formats. The target platform for the utility was high end Intel processor based personal computers running Windows NT.

Worked on three disk drive programs in the high performance hard drive division as both a generalist and as a SCSI firmware engineer. Utilizing a mixture of C and assembly (Motorola 68K, NEC V850) developed performance sensitive firmware in a complex environment that includes a real time operating system (RTOS) with limited resources. Task included but was not limited to initial board debug, implementing compression algorithm for flash, flash down loader, memory diagnostics, memory optimizations, SMART prediction algorithm, error logging functionality. Promoted from Design Engineer I to Design Engineer II in first year of

Developed Microsoft Access databases to track the equipment of the Quality Assurance department.