Sr Staff Electrical Engineer (Technical Leader I)
San Jose, Ca, Us
(acquisition of Scientific-Atlanta, Inc. in 2006)My role was to create custom SW/HW test solutions in an effort to validate & improve the quality of our digital ASIC designs. This position was very unstructured and required intense time management skills to complete a wide range of tasks.Validation/Debug• Developed exhaustive characterization studies on set-tops containing corner-process ASICs.• Developed low power studies to isolate ASIC energy consumption in a system.• Performed failure analysis on field returned set-top boxes with lab experimentation and programming.• Extensive bench testing and experimentation using logic analyzers, oscilloscopes, and protocol analyzers (USB/PCIe/wireshark).• Extensive PCB rework as needed for lab studies and experiments.Embedded SW• Developed extensive embedded software applications in C (Cygwin) to characterize and debug ASIC behavior in a system environment of a cable set-top box hosted by MIPS/SPARC processors.• Created custom embedded USB2.0 driver code based on EHCI specification to allow video playback and unique FAT32 implementation on engineering set-top box.• Developed PIC microcontroller code for LCD display and keypad control on complex FPGA platform.• Created several SPI to TCP/IP debuggers based on 8051 MCU.• Developed firmware that would allow a set-top to become a JTAG boundary scan tester.PCB design• Designed prototype PCB test-boards to support each new ASIC release, typically mated with a production set-top box allowing special instrumentation needed for engineering development.• Designed complex stand-alone prototype platforms around home gateway ASIC that were used for customer demonstrations and home trials. Design elements supported: I2C, SPI, SATA, PCIe, RS-232, DOCSIS, MoCA, Ethernet, DDR2, FLASH, USB, and JTAG.RTL design• RTL integration and verification of USB2.0 IP into home gateway ASIC.• Developed behavioral simulation tests in Verilog and SystemC for ASIC/FPGA.