Sr. Process Engineer
Current• Served as a Sr. lapping & polish process engineer to support the Lapping & Polish processes to meet the thickness target and uniformity criteria and insure the high product yield after demounting. Also, manage continuous wafer breakage & cleanliness improvement, and cost reduction activities by in-house slurry development and chemical saving by metal lift-off process development. • Developed the batch processes of lapping & polish process by custom-made Lapmaster tool to increase the throughput by 300% and identifying the critical THK & uniformity control parameter, such as photo resist baking Temp., new bonding wax selection / coating /bonding processes & setting the Spec. & SPC control limit to monitor in line. • Developed the 3-inch wafer bonding and demounting process with new wax to improve the wafer cleanliness and wafer breakage (=improving yield) • Also, fully support Wafer Scanner THK measurement tools, All-Win21 RTA annealing tools, CO2 Snow cleaning, Suss-CTR PR/Wax coating cluster (wafer bonding Prep.), eBeam Metallization tools, Track Metal Lift-off, thin InP wafer demounting/cleaning processes including writing the operation procedures and documentation, and setting the process window & operation criteria, hardware/fixture modification and back-up for scribe and cleave operation.• Implemented microscope inspection (VI) after demounting the wafer and feedback to the Fab. for the reject wafers and FA and CA on customer defects such as identifying root-cause of the 45-degree angle scratch, series of tester probe mark damage, and no die identification number problem.