BIOS development of Intel Atom base servers.

· 2015 - 2017: Sysdebug lead for Atom SoC, Debug coordinator for Atom based SoC for cloud/storage/ communication application, focal point to provide feedback for key milestones during validation life cycle. In charge to achieve the validation schedule and prioritization of the debug activities.· 2014 - 2015: Debug tools lead for Atom SoC, in charge of the debug tools for post-silicon validation these include debug probes, development and support of the Python debug environment. In charge of teaching and training multiple teams on the usage of the debug tools.· 2011 - 2014: Memory Buffers validation Eng. post silicon validation of the MB C104/2, C114/2 used on HPC segment. Working on the validation of DDR3, later in charge of the DDR4 interface working on the enablement and validation of RDIMMs/LRDIMMs. Leading a work group to speed up the enabling and validation of the DDR4 interface which includes multiple teams like design, functional validation, electrical validation and BIOS.

Working on post silicon validation for the C104/2 Scalable Memory Buffer. During this time, I was developing debug tools using Python, also helping with the debug and validation of JTAG and SMBus interfaces.

Working on pre-silicon validation for a video analytics coprocessor. Running and debugging regression tests content, providing support for the validation models and the test environment using System Verilog and System C.