Joseph Chang Email & Phone Number

Large-Scale Integrated Photonics Lab

San Jose, California, United States

● Responsible for owning and architecting RTL design to encompass the different peripheral interfaces including, but not limited to, I2C, SPI, UART and GPIO control for RFFE signals targeting the Kria SOM as an evaluation platform to verify the GPIO functionality of in-house small cell transceiver● Familiarity with Vitis software development workflow in generating platform specific components that include XSA and boot components to run accelerated firmware using custom PL device tree overlay on the Kria SOM

Raleigh-Durham-Chapel Hill Area

Wireless Platform Group● Implemented reference design using AMD’s Ultrascale+ GTY transceiver wizard configured for JESD204C NRZ with desired use-case from customers to deliver them an FPGA solution to aid with their development bring-up● Supported designing of individual modules, functional simulations on block level along with top-level design integration● Involved with technical team coordination across different regions for successful project completion and bug fixes● Developed automated hardware regression test scripts in Python to execute different JESD204C NRZ profiles supporting up to 32.5Gb/s to run on in-house evaluation platform board● Worked on FPGA designs targeting Virtex Ultrascale+ HBM device with experiences in SLR partitioning/pblock constraints to enable timing closure for designs operating at high speed clock frequency● Developed JESD204D (in support of PAM4) Transmit Link Layer for next-gen evaluation platform design

Sunnyvale, Ca

• Design, implementation and lab testing of sub-1GHz camera link application with SerDes on Zynq Ultrascale+• Participate in simulation and timing debug activities to support design with an external interface to RF transceiver device on the Zynq-7000 • Interface hand-code RTL with Simulink HDL autocode developed by system engineers for design development• Maintain common RTL design platform and implementation in VHDL and analyze/debug RTL design issues • Perform FPGA synthesis, place & route and timing constraints to achieve functional and performance goals• Develop FPGA design verification environment and test plans with techniques of constrained randomization and SystemVerilog assertions in OVM and UVM for both module and chip level verification• Create test cases, sequences, interface behavior prediction models and agents to resolve bugs found in the design and generate code and functional coverage reports for a given FPGA design

Centennial, Colorado, United States

• Developed VHDL test bench for Ethernet frame simulation • Breadboarded a LISN (line impedance stabilization network) for conducting military emission standards for electromagnetic compatibility on DC-DC converters for Blue Origin engine• Weekend on-call support for the manufacturing suppliers of flight boxes

Milpitas, Ca

• Collaborated with test engineers in performing root cause analysis, troubleshooting and resolving test yield problems on hardware validation of server systems• Ensured accurate record and test measurement data pertaining to the product parameters

Tainan City, Taiwan

Electrical Engineering Ms, Ic Design

Bachelor Of Science (Bs), Physics