Joseph Spanier Email & Phone Number

Senior FPGA designer with over 7 years experience with both Altera and Xilinx designs. Implemented for an advanced Power Quality Meter (Altera Cyclone Family) and for Radar Simulator (Xilinx Vertex Family) using VHDL. Familiarity with Cyclone V SoC, Quartus Prime, Modelsim, Intel SOC EDS, Xilinx ISE Design Suite, Verilog.Heavy Design experience in many areas including architect of a high end industrial Power quality meter with a tri-processor architectures and A/D acquisition system and 50 MHz sampling and power surge detection circuitry controlled by an FPGA, FPGA based multiple time synchronization including Precision Time Protocol (PTP) or SNTP or IRIG-B, F-4F FPGA based high-density video radar simulator, 4G LTE Cell Modem board, 100/10 base-T network board designs and other I/O board designs.C language Firmware port of Network stack for use on a 10 base-T network board.Altium and PCAD board design experienceDFM reviews of board designsMicrosoft Project used to plan and track development progress.

• 

  Senior Project Manager, Senior Digital Designer And Fpga Designer

  Electro Industries

  Dec 1999 - Oct 2019 - Brooklyn, Ny

• 

  The City College Of New York

  Electrical And Electronics Engineering