**Experienced developer focused on low power and high density SRAM circuit design and process integrationof advanced technologies. I have experience in the development of high density SRAM circuit from 5nm to3nm Tech. nodes. I am acquainted with knowledge regarding CMOS logic circuits / front-end and back-endprocess integration and yield enhancement learning. I have experience in project conduction / failure analysis/ reliability analysis / product qualification for mass production. Being a team player with stronginterpersonal communication skills, I am passionate building leading edge electronics.
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Sram Circuit Design EngineerTsmc Jan 2019 - PresentFocused on low power and high density SRAM circuit design and PPA assessment for advanced technologies. -
Principle Device And Reliability EngineerTsmc Nov 2017 - Nov 2018Led development teams, ranging from 2 to 5 cross-functional engineers per project; Focused on product development for the most advanced technology node, including performance gain and manufacturability.
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Process Integration EngineerTsmc Apr 2013 - Nov 2017Worked closely with engineers from multiple technical groups on logic CMOS development; Especially for the Core and IO CMOS. Experienced in full design flow from PCM design, circuit layout, tape-out, chip fabrication and testing.
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Teaching AssistantNational Taiwan University Sep 2006 - Jun 2010Taiwan
Joseph W. Education Details
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Opto-Electronics And Photonics
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Electrical And Electronics Engineering
Frequently Asked Questions about Joseph W.
What company does Joseph W. work for?
Joseph W. works for Tsmc
What is Joseph W.'s role at the current company?
Joseph W.'s current role is SRAM circuit designer at TSMC.
What schools did Joseph W. attend?
Joseph W. attended National Taiwan University, National Tsing Hua University.
Who are Joseph W.'s colleagues?
Joseph W.'s colleagues are Cheng-Chang Chiang, Hüseyin Kuzu, Zong-Jhan Yang, 夏董辉, Ritvik Agarwal, 潘建勳 Ch Pan, 張世鵬.
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