Joseph Kerth Email & Phone Number

Portland, Oregon, United States

Emulation and FPGA Prototyping

Built and managed a dedicated design verification team of 4 full time employees and 4 Contract Workers. Defined the verification strategy and test plan for a next-generation SoC chip targeting WiFi and PLC applications.Hands-on development of UVM-based verification environments and tests to verify GPP and DDR4 subsystems. Led cross-functional alignment of verification strategies with architects, design and software engineers, and managers.Enhanced chip-level simulation to support ATE generated testbenches to replicate ATE test failures for debug.Identified simulation improvements that resulted in reduction of SoC full chip simulation time from weeks down to days.

Executed both management and technical tasks in a leadership role for a validation organization. Responsible for talent growth and career guidance for new and experienced engineers. Defined project requirements, correlated them to company OKRs, and translated to individual responsibilities.Identified cross functional FPGA prototype requirements for each stage of the IP and SoC design lifecycle. Communicated program status, schedule, and risks to upper management.Maintained relationships with tool vendors and contributed to influencing tool development.Defined and researched both Xilinx and Stratix FPGA prototype strategies for future PCIe and CXL.io based accelerator IPs.Managed staff augmentation resources and complied with legal disclosure agreements and addendums.Led a pilot project to convert a Xilinx FPGA prototype model to a Stratix FPGA prototype model that provided confidence needed to make decisions on platform selection for future programs and relieving capacity constraints on platform availability. Migrated internal git repo to a remote secure github server for easier sharing and collaboration of FPGA Prototype collateral.

Owned execution and development of full FPGA prototype flow for HAPS Multi FPGA based models for several generations of the Intel QuickAssist (QAT) accelerator IP.Maintained the tool flow and updated Python, Perl, and TCL scripts when necessary while following standardized methodologies.Worked with software, fw, and validation engineers to establish a repeatable release methodology that included executing basic acceptance tests for tools and driver checkout as well as running sanity regression tests for validation. Developed SystemVerilog system-level modules that integrated FPGA and prototype platform components with top-level IP module interfaces. Owned simulation of FPGA top-level modules and wrote SystemVerilog and UVM based testbenches and tests to exercise the top-level modules.Integrated, configured, and extended vendor simulation and UVM environments for PCIe, AXI4, and AXI4-Stream based protocols.Frequently collaborated with design engineers to understand microarchitecture of IP and ensure RTL is FPGA friendly.Drove debug with validation engineers to help root cause test failures in the lab using multiple techniques such as FPGA instrumentation, PCIe Lecroy Protocol analyzer, and custom FW/SW. Integrated Simics virtual platform and FPGA transactor components for Hybrid FPGA use-cases.Developed PERL scripts to facilitate the implementation of FPGA friendly memories and synthesizable coverage constructs.

Developed test plans and Python based test content for validating a server chipset design. Executed test content in both pre-silicon and post-silicon environments including emulation, simulation, and linux. Collaborated with engineers from different internal organizations to help align validation strategies and methodologies with a focus on concurrency. Trained contractors to enable them to cover a significant portion of execution content. Performed work from pre-silicon through tape-in, followed by power-on and then volume validation.

Used Visual Studio to develop, execute, and debug C test code used for automated regression testing of firmware for a video processing board.Developed a C application to run load tests on a video processing board and collect and store the results. Assisted with miscellaneous production tasks.

Created postprocessor and simulation kits, using TCL, with full collision detection and gouging for 5-Axis Milling and Mill-Turn CNC machines for NX7.5 – NX8.5CMM programmer and operator of Zeiss Contura G2, using Calypso software and adhering to GD&T YSME 14.5M standardsBasic CNC operator including loading/unloading parts, setting coordinate and tool offsets, and tool maintenance.

Master Of Science (M.S.), Electrical Engineering, 3.8

B.S., Electrical Engineering