Josue F. Email and Phone Number
Design Engineer at Intel Corporation. Engineering professional working with Intel Federal on Government Contracts. Interested in the ASIC Design flow process for design and validation.Summa Cum Laude Graduate from the University of Texas at San Antonio, majored in Electrical Engineering with a Computer Concentration. IEEE-HKN UTSA President for two years and helped increase the member count in the process.Goals:Quality results.Challenge my peers.Continue to innovate and strive for success.Specialties: Programming Languages: VHDL, Verilog, C, C++, Perl, Python, Chameleon Code, C# , AssemblyApps: Microsoft Office, Microsoft Project, Visio, Cadence Orcad PSPICE, HSPICE, Cadence PCB Editor, Cadence Encounter, Magic VLSI, LabView, SimUAid, LogicAid, ModelSim, Xilinx ISE, Freescale Codewarrior, MATLAB, Simulink, Maple, Visual Studio, Borland C++, Adobe Suite, Windows, Linux, Unix, SynopsysElectronic Test Equipment: Oscilloscope, Multimeter, Function Generators, Spectrum Analyzers, Logic Analyzers, ATE's
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Component Design EngineerIntel Corporation Jun 2021 - PresentHillsboro, Oregon, United StatesDeveloping the next generation High Performance Computing Processor for Supercomputers, Graph Analytics/AI/Machine Learning SOCs as well as custom ASICs to partner with Xeon processors. -
Senior Product Development EngineerIntel Corporation Mar 2012 - Jun 2021Hillsboro, OregonResponsible for ensuring the testability and manufacturability of integrated circuits from the component feasibility stage through production ramp.Validated Intel Persistent Memory DIMM memory controller via testing such as ACIO Loopback, Boundary Scan, Leakage, VIX/VOX. Memories include DDR4, DDR5, LPDDR5, DDRT2 (up to 4800 MTs) in Pre Silicon and Post Silicon stages. Wafer and package HVM testing to test for manufacturing defects.Develop and Validate HSIO DDR Firmware on ATE and Bench DV Boards.Validated in Pre-Silicon RTL Simulation and Post Silicon activity for sPCH chipset testing interfaces such as PCIe, DMI, USB, SATA, P2P. Developed Data Collection Scripts via ATE's for various products with sPCH and Memory Controller/Buffers. Mass collection of Shmoo plots with post processing for visual representation and analysis.Develop Automation scripts in Pre-Silicon and Post Silicon environments in bash, python and perl. -
Research AssistantMultimedia And Mobile Signal Processing Laboratory Jul 2010 - May 2011Advisor: Dr. Sos Agaian• Purkinje cell 3D Reconstruction and Visualization System• Developed an image enhancement algorithm for image sequences on endothelial cells using fluorescence microscopy. Worked hand in hand with a Ph.D. student in the Biomedical Engineering Department.• Developed an algorithm for image enhancement for MRI image sequences using histogram equalization and de-noising procedures by the use of alpha trimmed mean.• MATLAB environment: cubic spline interpolation, non-linear diffusion filtering, spatial/frequency domain global image enhancement (Alpha Trimmed Mean filters, α-Rooting DCT-II Based image enhancement), local image enhancement (Un-sharp masking, Adaptive Contrast Enhancement)
Josue F. Education Details
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James Madison High School
Frequently Asked Questions about Josue F.
What company does Josue F. work for?
Josue F. works for Intel Corporation
What is Josue F.'s role at the current company?
Josue F.'s current role is Component Design Engineer at Intel Corporation.
What schools did Josue F. attend?
Josue F. attended The University Of Texas At San Antonio, James Madison High School.
Who are Josue F.'s colleagues?
Josue F.'s colleagues are Nidhi Kakkar, 李建华, Andrés Núñez, Karim Emad Morsy, Aishwarya Vadlamudi, Raj Shah, Yidnekachew (Yidnek) Mekonnen.
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5salemstate.edu, salemstate.edu, axis.com, salemstate.edu, clearmotion.com
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1reatapharma.com
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Josué F Rodrigues
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