Joy Paul Email and Phone Number

Responsible for driving timing closure on next-generation Atom CPUs in leading process nodes. This involves defining methodology, data mining, running/triaging timing models, and ensuring that the design converges to meet project goals.Responsible of all aspects of Physical Design for Integer execution and BUS partition in recent process nodes of Atom CPUs. Performed synthesis, APR, eco fixes, signoff to the tape in. Converged timing & power and ensured reliability & physical verification.

Automated and enhanced Full Chip Verification (Timing, Noise, FEV, DRC, LVS etc) flow by combination of Perl, TCL, CSH & Makefile scripts. Validated and deployed UPF based Simultaneous Multi-Voltage Analysis in Full Chip Timing (FCT). Released official Full Chip Timing (FCT) in multiple corners to close new timing paths & electrical violations. Drive design Engineer to point and root cause of the failed paths by providing concise information from parsed timing reports by perl/tcl scripts and by using SQL queries from timing databases.

Timing lead for multiple functional units, driving circuit, integration and logic team to close timing paths by providing best solution possible and writing various scripts to customize reports to have easily noticeable but full picture of timing paths for its closure.Circuit lead of non-cacheable & core interface unit. This involves designing custom macros based on static logic and its layout; making sure macros satisfies unit & chip integration goals, passed through design methodology, circuit topology and test verification. Making sure macros meet noise and power targets.

Custom designing data path schematics from RTL code, simulating critical path and dynamic part of circuits to ensure timing and functionality, de-skewing CLOCK domains and providing layout guidance by deciding the usage of metal and its templates.Synthesizing control schematics, creating constraint files, resolving timing and loading issues; Place & routing synthesized design, extracting min & max caps and feeding them to stating timing analyzer tools for coupling, race and critical path flagging.