Jong Pil Lee Email & Phone Number

 20 years’ experience in SOC development and design flows Author of synthesis, timing signoff flow of Exynos processors. Currently leading SOC design implementation of Samsung’s next generation Exynos processors. – RTL synthesis, Static Timing Analysis, On-chip variation analysis, Sign-off methodology, Physical Design, and interfacing with foundry, and EDA vendors. Developed design methodology and framework supporting multimode, multicorner, and hierarchical timing closure Received three Samsung Electronics awards including Best Accomplishment Award