Senior Analog Mixed-Signal Ic Design Engineer
CurrentAnalog, mixed-signal, RF/Microwave and digital IC design, verification, and silicon characterization.Architect and designer of crucial components of the company's product line (PLL and SerDes IP) in FinFET and planar nanometer CMOS technologies from multiple foundries. From concept, through schematics, layout supervision, post-layout verification, tapeout, and laboratory characterization, to mass production customer support.Recent designs include 32Gbps SerDes RX with CTLE, T-Coils, DFE, Current-steering DACs, Adaptation RTL, etc. With specific variants for low latency, PON, and ultra-low power multi-protocol (for a large FPGA vendor), on 28nm planar, 16nm, 12nm and 6nm FinFET. Earlier work includes ring-VCO and LC-VCO PLLs, and some PLL applications (Multi-channel pulse DAC for augmented reality environment mapping and Digital PLL loops).Developer of CAD tools for internal design/verification flows and high-speed simulation methods for complex systems and circuits. Significant contributor in the development and growth of the company, including methodologies, documentation, mentoring, and computational infrastructure. Have led and been involved in several R&D projects.
