Jeff Buchanan Email & Phone Number

Irvine Cal

Member of Verification Team on 65 nm low latency, low power 10Gb Ethernet Controller ASIC development.Object Oriented Design and Implementation in System Verilog of IPv4/IPv6 packet generation for 10Gb Ethernet controller chip Test bench.Developed the Ethernet Packet Generation of pseudo-random packets to be used in either User Directed Mode and/or.

Responsible for overall existing system digital design, debug, and ultimate delivery, including all upgrades, simulations, and modifications.Initiated the TCP/IP Ethernet interface addition for the Navy's Data Transfer System (DTS) Switch.Enhanced the NTDS to High Speed Serial path to allow for NTDS type C, and significantly decreased the error rate by a.

Oversaw the hardware development of a modular Home Gateway/ Router (Consumer Electronics) based on Intel's newly released IXP425 processor.Simultaneously managed local prototype with design to be used for Taiwan based ODM/OEM partner.

Developed ASIC and emulation validation tests for a RAID cache controller ASIC.Generated and implemented the test plan for the hardware Linked List and Cross Point Switch modules utilizing all seven embedded custom microprocessors. The tests were designed for the regression and emulation environments.Developed a Verilog test bench and debugged the serial.

Responsible for overall existing system digital design, debug, and ultimate delivery, including all upgrades, simulations, and changes.Lead engineer for the digital hardware development and production of the fiber channel NTDS computer switch.Design includes custom digital boards with 10 x 10k30 240 pin FPGAs (VHDL) and 20 mixed CPLDs (VHDL), and a.

Led portions of the implementation and delivery of two generations of extremely sensitive Digital Receivers for NASA's Deep Space Satellite Communications (down at -180 dBm). From Requirements through Design, Integration, Test, and Final System Checkout.Responsible for various portions of the design of high-speed (160 MHz) 200k gate GaAs ASICs (then state.

Designed and implemented the GPS `P' and `CA' code correlator / integrator standard cell ASIC that performed "Right the first Time" using Zymos's Zypsim simulator and Primos OS.Designed and implemented the GPS P-code generator gate array, which worked "Right the first time."Participated in the development of the GPS receiver's Interface Gate Array and the.

Bsee, Electrical Engineering

Education record

CONTINUING EDUCATION and TRAINING: Verilog, VHDL, C, C++, Digital Signal Processing, Java, Project Engineering