Jeff Buchanan Email & Phone Number

Irvine Cal

Member of Verification Team on 65 nm low latency, low power 10Gb Ethernet Controller ASIC development.Object Oriented Design and Implementation in System Verilog of IPv4/IPv6 packet generation for 10Gb Ethernet controller chip Test bench.Developed the Ethernet Packet Generation of pseudo-random packets to be used in either User Directed Mode and/or "constrained random stimulus packet generator" Mode. This packet generator allows such controlled variations in test packets as packet type (ICMP, ARP, SNAP, raw Ethernet, IPv4, IPv6, TCP, UDP, etc.), length (Jumbo packets), header, and predetermined errors

Responsible for overall existing system digital design, debug, and ultimate delivery, including all upgrades, simulations, and modifications.Initiated the TCP/IP Ethernet interface addition for the Navy's Data Transfer System (DTS) Switch.Enhanced the NTDS to High Speed Serial path to allow for NTDS type C, and significantly decreased the error rate by a factor of 100.Isolated intermittent error source and modified the FPGA design to increase the reliability and production yield by 30 percent of the DTS Extender-Bridge-Modules.Lead Engineer for next generation FPGA architecture and serdes (1, 2, Gbps) replacement investigation.Test and characterization of Xilinx Virtex II pro/Xilinx-Virtex 4FX, Lattice's Orca and SC FPGAs.

Oversaw the hardware development of a modular Home Gateway/ Router (Consumer Electronics) based on Intel's newly released IXP425 processor.Simultaneously managed local prototype with design to be used for Taiwan based ODM/OEM partner.

Developed ASIC and emulation validation tests for a RAID cache controller ASIC.Generated and implemented the test plan for the hardware Linked List and Cross Point Switch modules utilizing all seven embedded custom microprocessors. The tests were designed for the regression and emulation environments.Developed a Verilog test bench and debugged the serial bus protocol module for the Web TV ASIC.Simulated, debugged, and modified the JTAG Boundary Scan insertion, ATPG and parametric test-benches for the FPP ASIC.Processed the FPP ASIC through LSI Logic's `Flex stream' methodology through successful chip sign-off.

Responsible for overall existing system digital design, debug, and ultimate delivery, including all upgrades, simulations, and changes.Lead engineer for the digital hardware development and production of the fiber channel NTDS computer switch.Design includes custom digital boards with 10 x 10k30 240 pin FPGAs (VHDL) and 20 mixed CPLDs (VHDL), and a controller board with a MIPS R3000 microprocessor and concurrent PCI, Fiber channel, and VME high-speed bus interfaces.Process driven: instituted early simulation, configuration control, test procedures, and enforced unit testing.

Led portions of the implementation and delivery of two generations of extremely sensitive Digital Receivers for NASA's Deep Space Satellite Communications (down at -180 dBm). From Requirements through Design, Integration, Test, and Final System Checkout.Responsible for various portions of the design of high-speed (160 MHz) 200k gate GaAs ASICs (then state of the art wafer and process technology Vitesse).Member of the Orbital Very Long Baseline Interferometry tiger team and received a NASA Commendation for Outstanding Achievement for finding a flaw in the signal processing. The subsequent fix allowed NASA to meet its data recovery commitments.Managed both the ASIC Foundry and Board Level Subcontracting to ensure the smooth integration of ASIC and printed wiring board design during the manufacture of functional assemblies.Assigned to accelerate the development of the Large Virterbi Decoder to support the Mars Pathfinder mission. Led the subsystem integration of the ASICs, FPGAs, Pwa's and software to meet the delivery.

Designed and implemented the GPS `P' and `CA' code correlator / integrator standard cell ASIC that performed "Right the first Time" using Zymos's Zypsim simulator and Primos OS.Designed and implemented the GPS P-code generator gate array, which worked "Right the first time."Participated in the development of the GPS receiver's Interface Gate Array and the Course Acquisition/Numerically Controlled Oscillator ASICs.Received a commendation for a first prototype design completed ahead of schedule with no errors. Presented paper at the 1984 Valid Logic Worldwide Users Conference.

Bsee, Electrical Engineering

Education record

CONTINUING EDUCATION and TRAINING: Verilog, VHDL, C, C++, Digital Signal Processing, Java, Project Engineering