Jeffrey Schaver
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Jeffrey Schaver Email & Phone Number

Digital Design Engineering Manager at Silergy Technology at Silergy Corp
Location: Irvine, California, United States 9 work roles 1 school
1 work email found @silergy.com LinkedIn matched
✓ Verified Jun 2026 4 data sources Profile completeness 100%

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Current company
Role
Digital Design Engineering Manager at Silergy Technology
Location
Irvine, California, United States
Company size

Who is Jeffrey Schaver? Overview

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Quick answer

Jeffrey Schaver is listed as Digital Design Engineering Manager at Silergy Technology at Silergy Corp, a company with 147 employees, based in Irvine, California, United States. AeroLeads shows a work email signal at silergy.com and a matched LinkedIn profile for Jeffrey Schaver.

Jeffrey Schaver previously worked as Digital Design Engineering Manager at Silergy Corp and Principal Design Engineer at Silergy Corp. Jeffrey Schaver holds B.S., Electrical And Computer Engineering from The University Of Texas At Austin.

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Email format at Silergy Corp

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{first}.{last}@silergy.com
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Profile bio

About Jeffrey Schaver

Extensive background in the design of MCUs and other embedded processor products. Experienced in digital design, chip-level RTL to GDS back end flow, product specification, evaluation, and debug. Design efforts include mixed-signal SoCs, memory controllers, clock generation, USB, system management IP as well as other embedded processor products.Specialties: RTL design, low power techniques, synthesis and timing analysis, formal verification, chip integration, Cadence EDA tools, Verilog and SystemVerilog, Tcl, Perl, C, assembly programming, and project leadership.

Listed skills include Asic, Rtl Design, and Low Power Design.

Current workplace

Jeffrey Schaver's current company

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Silergy Corp
Silergy Corp
Digital Design Engineering Manager at Silergy Technology
sunnyvale, california, united states
Website
Employees
147
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9 roles · 34 years

Jeffrey Schaver work experience

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Digital Design Engineering Manager

Current

Provide technical contributions and management for the design of mixed-signal SoC products for the electricity metering and energy measurement markets.

2017 - Present ~9 yrs 5 mos

Principal Design Engineer

Project and design lead. Silergy Technology acquired the mixed-signal SoC business from Maxim Integrated that serves the electricity metering and energy measurement markets in March 2016.

2016 - 2017 ~1 yr

Principal Member Of Technical Staff

Project lead for the design and implementation of mixed-signal SoCs for the electricity metering markets.

2010 - 2016 ~6 yrs

Senior Staff Design Engineer

Teridian Semiconductor Corporation

Design and implementation of 4th generation mixed-signal SoCs for the electricity metering markets. Teridian Semiconductor Corp. was acquired by Maxim Integrated Products in May 2010.

2009 - 2010 ~1 yr

Member Of Technical Staff

Headed design team of six engineers to develop clock generation IP including a PLL, FLL, internal reference clocks, clock detector, and lock detector, performing logic design and supporting global teams with IP integration. Spearheaded the front end integration activities for test vehicle used to migrate proprietary nonvolatile memory technology embedded.

2004 - 2009 ~5 yrs

Design Contractor

Created and implemented cost reduction plan for the 68HC908QY4 MCU family that included die area reduction, robust static timing analysis, and functional verification. Redesigned legacy hard IP into Verilog RTL and created Synopsys Liberty models for other legacy hard IP for overall die area savings and thorough chip-level static timing analysis.

2003 - 2004 ~1 yr

Staff Design Engineer

Trimedia Technologies

Performed logic synthesis and timing analysis of TriMedia CPU and peripheral IP used on test vehicles, addressing all issues to meet area, timing, and testability goals. Setup and maintained configuration management tool used company wide for all design IP and wrote documentation for TriMedia IP customer ASIC usage.

2000 - 2001 ~1 yr

Senior Design Engineer

Designed IP blocks for use in HC08 and HC05 MCUs including USB, J1850, clock generation, and ADC. Worked with teams on design of the 56800E DSP and S12 CPU cores and designed external memory controller for the 56800E. Design team member for numerous consumer and automotive MCUs including 68HC908KL8, 68HC708AX48, and 68HC05JJ6.

1993 - 2000 ~7 yrs

Engineering Intern

Ibm

Conducted comprehensive testing of initialization software for RS/6000 workstation products and maintained software test lab in the Advanced Workstations Division while completing degree.

1992 - 1993 ~1 yr
Team & coworkers

Colleagues at Silergy Corp

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1 education record

Jeffrey Schaver education

FAQ

Frequently asked questions about Jeffrey Schaver

Quick answers generated from the profile data available on this page.

What company does Jeffrey Schaver work for?

Jeffrey Schaver works for Silergy Corp.

What is Jeffrey Schaver's role at Silergy Corp?

Jeffrey Schaver is listed as Digital Design Engineering Manager at Silergy Technology at Silergy Corp.

What is Jeffrey Schaver's email address?

AeroLeads has found 1 work email signal at @silergy.com for Jeffrey Schaver at Silergy Corp.

Where is Jeffrey Schaver based?

Jeffrey Schaver is based in Irvine, California, United States while working with Silergy Corp.

What companies has Jeffrey Schaver worked for?

Jeffrey Schaver has worked for Silergy Corp, Maxim Integrated Products, Teridian Semiconductor Corporation, Freescale Semiconductor, and Motorola Semiconductor.

Who are Jeffrey Schaver's colleagues at Silergy Corp?

Jeffrey Schaver's colleagues at Silergy Corp include 夏春新, Hung Shou Nien, 瞿建明, Henrik Malmström, and Fish Kao.

How can I contact Jeffrey Schaver?

You can use AeroLeads to view verified contact signals for Jeffrey Schaver at Silergy Corp, including work email, phone, and LinkedIn data when available.

What schools did Jeffrey Schaver attend?

Jeffrey Schaver holds B.S., Electrical And Computer Engineering from The University Of Texas At Austin.

What skills is Jeffrey Schaver known for?

Jeffrey Schaver is listed with skills including Asic, Rtl Design, and Low Power Design.

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