Jeffrey Schaver Email & Phone Number

Provide technical contributions and management for the design of mixed-signal SoC products for the electricity metering and energy measurement markets.

Project and design lead. Silergy Technology acquired the mixed-signal SoC business from Maxim Integrated that serves the electricity metering and energy measurement markets in March 2016.

Project lead for the design and implementation of mixed-signal SoCs for the electricity metering markets.

Design and implementation of 4th generation mixed-signal SoCs for the electricity metering markets. Teridian Semiconductor Corp. was acquired by Maxim Integrated Products in May 2010.

Headed design team of six engineers to develop clock generation IP including a PLL, FLL, internal reference clocks, clock detector, and lock detector, performing logic design and supporting global teams with IP integration. Spearheaded the front end integration activities for test vehicle used to migrate proprietary nonvolatile memory technology embedded with V1 ColdFire core into 90nm CMOS technology node. Developed and implemented low power architecture changes to decrease overall current consumption in next generation S08 and V1 ColdFire MCU products. Led back-end design teams for MC9S08EL32, 68HC908AZ60A, MCUs performing IP integration, synthesis, placement and routing, static timing analysis and LVS. Designed system integration IP and performed static timing analysis for MC9S08LL16 MCU. Trained and mentored design engineers located in China on design tool set and methodologies to increase quality and reduce cycle time.

Created and implemented cost reduction plan for the 68HC908QY4 MCU family that included die area reduction, robust static timing analysis, and functional verification. Redesigned legacy hard IP into Verilog RTL and created Synopsys Liberty models for other legacy hard IP for overall die area savings and thorough chip-level static timing analysis.

Performed logic synthesis and timing analysis of TriMedia CPU and peripheral IP used on test vehicles, addressing all issues to meet area, timing, and testability goals. Setup and maintained configuration management tool used company wide for all design IP and wrote documentation for TriMedia IP customer ASIC usage.

Designed IP blocks for use in HC08 and HC05 MCUs including USB, J1850, clock generation, and ADC. Worked with teams on design of the 56800E DSP and S12 CPU cores and designed external memory controller for the 56800E. Design team member for numerous consumer and automotive MCUs including 68HC908KL8, 68HC708AX48, and 68HC05JJ6.

Conducted comprehensive testing of initialization software for RS/6000 workstation products and maintained software test lab in the Advanced Workstations Division while completing degree.