Digital Design Engineering Manager
CurrentProvide technical contributions and management for the design of mixed-signal SoC products for the electricity metering and energy measurement markets.
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@silergy.com
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Jeffrey Schaver is listed as Digital Design Engineering Manager at Silergy Technology at Silergy Corp, a company with 147 employees, based in Irvine, California, United States. AeroLeads shows a work email signal at silergy.com and a matched LinkedIn profile for Jeffrey Schaver.
Jeffrey Schaver previously worked as Digital Design Engineering Manager at Silergy Corp and Principal Design Engineer at Silergy Corp. Jeffrey Schaver holds B.S., Electrical And Computer Engineering from The University Of Texas At Austin.
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Extensive background in the design of MCUs and other embedded processor products. Experienced in digital design, chip-level RTL to GDS back end flow, product specification, evaluation, and debug. Design efforts include mixed-signal SoCs, memory controllers, clock generation, USB, system management IP as well as other embedded processor products.Specialties: RTL design, low power techniques, synthesis and timing analysis, formal verification, chip integration, Cadence EDA tools, Verilog and SystemVerilog, Tcl, Perl, C, assembly programming, and project leadership.
Listed skills include Asic, Rtl Design, and Low Power Design.
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Provide technical contributions and management for the design of mixed-signal SoC products for the electricity metering and energy measurement markets.
Project and design lead. Silergy Technology acquired the mixed-signal SoC business from Maxim Integrated that serves the electricity metering and energy measurement markets in March 2016.
Project lead for the design and implementation of mixed-signal SoCs for the electricity metering markets.
Design and implementation of 4th generation mixed-signal SoCs for the electricity metering markets. Teridian Semiconductor Corp. was acquired by Maxim Integrated Products in May 2010.
Headed design team of six engineers to develop clock generation IP including a PLL, FLL, internal reference clocks, clock detector, and lock detector, performing logic design and supporting global teams with IP integration. Spearheaded the front end integration activities for test vehicle used to migrate proprietary nonvolatile memory technology embedded.
Created and implemented cost reduction plan for the 68HC908QY4 MCU family that included die area reduction, robust static timing analysis, and functional verification. Redesigned legacy hard IP into Verilog RTL and created Synopsys Liberty models for other legacy hard IP for overall die area savings and thorough chip-level static timing analysis.
Performed logic synthesis and timing analysis of TriMedia CPU and peripheral IP used on test vehicles, addressing all issues to meet area, timing, and testability goals. Setup and maintained configuration management tool used company wide for all design IP and wrote documentation for TriMedia IP customer ASIC usage.
Designed IP blocks for use in HC08 and HC05 MCUs including USB, J1850, clock generation, and ADC. Worked with teams on design of the 56800E DSP and S12 CPU cores and designed external memory controller for the 56800E. Design team member for numerous consumer and automotive MCUs including 68HC908KL8, 68HC708AX48, and 68HC05JJ6.
Conducted comprehensive testing of initialization software for RS/6000 workstation products and maintained software test lab in the Advanced Workstations Division while completing degree.
Other employees you can reach at silergy.com. View company contacts for 147 employees →
夏春新
Colleague at Silergy CorpSingapore, Singapore
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HS
Hung Shou Nien
Colleague at Silergy CorpContact Info, United States
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瞿
瞿建明
Colleague at Silergy CorpChina, China
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Henrik Malmström
Colleague at Silergy CorpStockholm, Stockholm County, Sweden, Sweden
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Fish Kao
Colleague at Silergy CorpTaiwan, Taiwan, Province Of China
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WL
Wei-Hsiang Lien
Colleague at Silergy CorpHsinchu City, Taiwan, Taiwan, Taiwan, Province Of China
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JM
Jerry Meng
Colleague at Silergy CorpChangzhou-Wuxi-Suzhou Metropolitan Area, China
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IT
Ian Tsai
Colleague at Silergy CorpTaiwan, Taiwan, Province Of China
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Brian Hegna
Colleague at Silergy CorpAptos, California, United States, United States
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AD
Anjin Du
Colleague at Silergy CorpChina, China
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Jeffrey Schaver works for Silergy Corp.
Jeffrey Schaver is listed as Digital Design Engineering Manager at Silergy Technology at Silergy Corp.
AeroLeads has found 1 work email signal at @silergy.com for Jeffrey Schaver at Silergy Corp.
Jeffrey Schaver is based in Irvine, California, United States while working with Silergy Corp.
Jeffrey Schaver has worked for Silergy Corp, Maxim Integrated Products, Teridian Semiconductor Corporation, Freescale Semiconductor, and Motorola Semiconductor.
Jeffrey Schaver's colleagues at Silergy Corp include 夏春新, Hung Shou Nien, 瞿建明, Henrik Malmström, and Fish Kao.
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Jeffrey Schaver holds B.S., Electrical And Computer Engineering from The University Of Texas At Austin.
Jeffrey Schaver is listed with skills including Asic, Rtl Design, and Low Power Design.
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