• Chair of Dept. of Intelligent Information Convergence in Graduate School (Feb 2022 – Present)• Chair of Dept. of Electrical and Electronic Engineering (Feb 2022 – Present)• Faculty member of Dept. of Electrical and Electronic Engineering (Mar 2020 – Present)

• PI/PD & DFT architecting, for flagship ARM CPU/GPUs for Galaxy S2~S21.• Specialties in Synthesis, P&R/PV, STA/ECO, DFT/ATPG, Redhawk-based PI for Func/Scan, etc.• [PI/PD] - taped-out over 20 projects using DC-ICC1/2 or FC flow. - achieved maximum clock frequency in any process technologies (5nm~over 100nm). - succeeded P&R in terrible routing congestion from high cell utilization over 80%. - minimizing leakage/dynamic power consumption in Synthesis/P&R/ECO.• [DFT architecting] - taped-out over 15 projects using Synopsys DFT flow. - achieved and signed-off Samsung's first 3-level hierarchical DFT (GPU_TOP--ShaderCore--SubCore). - low-power test pattern generation and physical ECO to meet Scan static/dynamic IR-drop.