Juahn L. Email & Phone Number

- SOC Desgin Verificaiotn with UVM - IP experiences : SPI, JTAG, eFlash, Ethernet, AXI4 width converter(By default, the CPU side uses the C,C++ code and connects VIPs to each IP in the SOC to run the simulation.) - Manually creating UVM environments [systemverilog] - Creating auto TBgen(UVM) environment for complex SOC with python, jinja. - Functional coverage check - Familiar with raising coverage percentage with synopsys vip too. - Synopsys VCS, Verdi, DC experiences- Developing methodology which reduce RTL Simulation runtime [Patent] - Using SystemVerilog save/restore - Using Linker scripts- SOC Design with Chisel3/Rocketchip generator [scala] - Top integration experience with SOC for data center - Integrate various subsystems with Rocketchip Diplomacy - Design muxtree, PAD controllerI am familiar with verilog, systemverilog, and UVM. Of course, language and methodology are just tools, but I have the ability to implement the desired logic design and verification environment design using those tools. Furthermore, I am also familiar with creating the desired environment using json-type data using jinja, python, bash, and makefile. In addition to the technical aspects, I am familiar with communicating, writing, and working in English.

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  Engineer

  Semifive

  Sep 2021 - Present - 대한민국 경기도 성남

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  숭실대학교

  Physics