Judy J Email and Phone Number

• Simulated block transistor level analog circuit (i.e. regulator) with HSPICE and Spectre via ADE. Verified the power sequence and functionality of the circuit. • Simulated top level design (analog and digital blocks) with HSIM. Job included checking floating gate detection, transistor overstress condition, leakage DC current path and power sequence. • Generated verilog netlist for analog IP in varies major projects.• Working on the Perl scripts to make data extraction (testbench) automation.

• QAed major IPs and prepared checklist for major projects. IPs include STDCELL, IO, Single/Dual port RAM/ROM, custom power isolation cells, USB and etc from various vendors (TSMC, Tower, UMC). Job included functional verification (both cdl netlist and verilog model), DRC/LVS, SDF annotation checking, and views consistency checking. • Customized the existing IP based on design teams’ needs. Jobs included verilog model updating, layout/cdl netlist modification, LEF view generation and etc. • Designed a padring layout for projects planning in 0.13um technology. Run DRC/LVS from top chip view. • Established cell characterizations, also enhance the script for characterization and QA automation. • Preparing HSPICE simulation datasheet to support analog design team.

• Managed, coordinated and provided administrative support for Dean, and faculty members. Responsibilities include event planning, slides preparation, scholarship preparation, providing help in various desktop applications.

• Designed a set of 4,8,12 mA programmable IO using HSPICE and Virtuoso simulation tools. Project involved in defining specification, tracing CDL file, capturing schematic, and running circuit simulation.• Designed a HSPICE deck to verify 8mA bi-directional buffer power consumption with 0.25um and 0.18um technology.• Characterized customized embedded single/dual port synchronous SRAM with requested frequencies by using Start-Sim and HSPICE. Released to cell library.• Designed script to generate IBIS model for simulation of board and components.• Designed and characterized a set of delay cells for the OTI9510 project in a timely manner. Delivered items include the qualified GDS/CDL model, balanced tr/tf timing and a completed cells datasheet.

• Maintained and enhanced IC circuit device of the handheld GPS emergency tracker products. Familiar with the equipment of DMM (Digital Multi-Meter) and oscilloscope. • Worked with design and manufacturing team members to resolve technical issues in timely manner.