I worked on full-chip functional model testing for an internal IP.

I proposed a design for dynamic adaptive mapping between addresses and cache lines to support varying locality between and within applications. I summarized my research findings to prospective undergraduate researchers by presenting a poster for the Fall 2022 Grainger Research Fair.

I supported students in digital design concepts and SystemVerilog using an FPGA. I also guided students’ implementation with testbenches, simulation, and synthesis tools.

I addressed gaps in student comprehension through guided problem sets on PrairieLearn, a platform for online assessments which supplemented lecture material every week. Creating a problem set required a proposal, wireframe, then implementation through HTML and Python. Throughout this process, I would receive (and give) feedback to the rest of my team. Once the draft was crafted, I carefully tested outgoing problems on a variety of potential submissions before deployment.

Over the summer, I researched unit specification, PCIe protocol, and UVM to develop functional coverage for unit interface. I was also responsible for integrating new scripts into the existing testing infrastructure to easily display metrics of regressions.

I implemented full stack features on an internal network traffic monitoring tool to enable search customization for users. This meant I primarily worked on front end features but also studied time series data analysis to increase the tool’s accuracy. While on the team, I also diagnosed an error that was causing delays with the graphical interface, enhancing our customer’s reliability with web application.

I taught concepts in math and English grammar to a classroom of elementary students.

I facilitated communication between classroom and administration. I also kept tabs on individual student performance to report to the teacher and or parents.