Jun Chen Email & Phone Number

>> 15+ one-time success tape-outs and 8+ year ASIC physical design experience.>> Hand-on project experience across various foundries (TSMC, GF, ST, SEC and SMIC) and processes (Bulk 65nm/40nm/28nm, FDSOI 28nm/22nm, FinFET 14/12/10/7nm).>> Strong experience in all aspects of physical design from netlist handoff to GDS tape out, including floor planning, power grid planning, IO planning, pin assignment, complex clock tree synthesis, placement and route, timing and SI analysis and closure, DRC/DFM check and fixing, IR/EM analysis, Formality and VCLP.>> Rich experience on low power design, including multi-voltage design, untra-low votlage deisgn, power-gated design with 30+ power domain.>> Working knowledge on high performance processor core PPA evaluation and optimization, including CPU, GPU, ZSP, HD Video Encoder and Decoder.>> Some knowledge on SoC design, DFT, Package design, Testing and FA.

Listed skills include Synthesis, Low Power Design Implementation, Place&Route, Complex Clock Tree Synthesis, and 6 others.

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  Senior Manager

  芯原

  Jul 2013 - Present - Shanghai