- MOSFET and Bipolar device development with 65nm technology . Mask design for width, length, LOD, well proximity effect, gate capacitance, reliability and mismatch. . Coordination of the fab process split and automated electrical test on the fabricated wafers. . Silicon data analysis and modeling spec extraction for the parameters; Vt, saturation Ids, linear Ids, leakage, forward & reverse bias effect and breakdown voltage each for cold/room/high temperature. . SPICE model… Show more - MOSFET and Bipolar device development with 65nm technology . Mask design for width, length, LOD, well proximity effect, gate capacitance, reliability and mismatch. . Coordination of the fab process split and automated electrical test on the fabricated wafers. . Silicon data analysis and modeling spec extraction for the parameters; Vt, saturation Ids, linear Ids, leakage, forward & reverse bias effect and breakdown voltage each for cold/room/high temperature. . SPICE model creation based on the extracted spec, then SPICE simulation/verification of other bias/operation condition which was not included in electrical test.. Electrical SPC control target proposal based on Si and model data.. SPC system setup to monitor Cpk, Z and device properties as lots go through the fab.. Run bench characterization of the Si device for the electrical test data verification and failure analysis- High voltage MOSFET development* Drain-extended structure . Development of the drain extended high voltage MOSFET on 2.5V(65nm STI process) and 3.3V(0.15um STI process & 0.4um LOCOS process) platforms. . TCAD optimization with baseline process and device structure design for the required device property.. Design rule and layer integration verification through DRC, LVS run.. Data analysis per STI length, channel length/width, gate overlap and gate extension over STI.. Run minimum design rule verification project including well-well, drain-tap and active rounding effect . Created automated electrical test program for Vt, Ids, leakage, substrate current, output resistance, sub bias effect and breakdown property.. Run bench characterization of the Si device for the electrical test data verification and failure analysis.* LD and JFET drain structure . LD drain MOSFET development for low gate capacitance SONOS memory cell application on 2.5V STI process.. JFET-drain structure design for the application of high well doping process with no process change. Show less