Jun Tan

Jun Tan Email and Phone Number

高级经理 @ 清微智能
Shanghai, China
Jun Tan's Location
Pudong, Shanghai, China, China
Jun Tan's Contact Details

Jun Tan work email

About Jun Tan

Specialties: ASIC design, P&R , STAFamiliar with FPGA and FPGA software systemTcl, Perl, C, C++

Jun Tan's Current Company Details
清微智能

清微智能

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高级经理
Shanghai, China
Website:
tsingmicro.com
Employees:
18
Jun Tan Work Experience Details
  • 清微智能
    高级经理
    清微智能
    Shanghai, China
  • 清微智能
    高级经理
    清微智能 Oct 2022 - Present
    中国 上海市
    BE DESIGN
  • Alibaba Group
    Timing Signoff Leader/Manager
    Alibaba Group Nov 2019 - Present
    中国 上海市 浦东新区
  • Globalfoundries
    Smts
    Globalfoundries Jul 2015 - Present
    Shanghai City, China
    Taped out 5 chips at 7nm , 14nm FinFet technology nodes and 32nm, 22nm FDSOI . Master STA analysis and physical implementationHands-on experience on TOP/block level physical implementation and timing analysis/closure.Have deep understanding of ASIC design methodology. Hands-on Methodology architect and development experience for the whole 22nm FDSOI physical implementation flow on ICC2 and Innovus. Very good at scripting .Master… Show more Taped out 5 chips at 7nm , 14nm FinFet technology nodes and 32nm, 22nm FDSOI . Master STA analysis and physical implementationHands-on experience on TOP/block level physical implementation and timing analysis/closure.Have deep understanding of ASIC design methodology. Hands-on Methodology architect and development experience for the whole 22nm FDSOI physical implementation flow on ICC2 and Innovus. Very good at scripting .Master Innovus/ICC/PT/Calibre2018-2019 CEO Award Show less
  • Ibm
    Advisory Chip Design Engineer
    Ibm Jan 2014 - Jun 2015
    Shanghai City, China
    STA / Physical Implementation, Full chip timing owner and block physical designer.
  • Amd
    Sr. Asic Design Engineer
    Amd Sep 2011 - Jan 2014
    Shanghai, China
    Taped out 4 28nm GPU chip.Took the role as a Block Owner, both physical design and timing closure.Block PD Leader, Full chip timing ownermaster ICC, PT, Encounter, Calibre, Olympus
  • Ibm
    Asic Design Engineer
    Ibm Jul 2008 - Sep 2011
    Shang Hai
    IBM 2008/07 till nowTapped out 4 OEM chips (65nm to 22nm) in past 3 years, 2 chips on goingphysical design and methodology developmentfullchip timing,focus on timing analysis and closure
  • Sony
    Software Engineer Intern
    Sony Jun 2007 - Sep 2007
    Sony Shanghai R&D Center
    UI development on Eclipse RCP (Java)

Jun Tan Skills

C++ C Perl Tcl Asic Fpga Static Timing Analysis Linux Physical Design

Jun Tan Education Details

Frequently Asked Questions about Jun Tan

What company does Jun Tan work for?

Jun Tan works for 清微智能

What is Jun Tan's role at the current company?

Jun Tan's current role is 高级经理.

What is Jun Tan's email address?

Jun Tan's email address is ms****@****ail.com

What schools did Jun Tan attend?

Jun Tan attended Fudan University, Southeast University.

What skills is Jun Tan known for?

Jun Tan has skills like C++, C, Perl, Tcl, Asic, Fpga, Static Timing Analysis, Linux, Physical Design.

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