Collaborated with CPO to develop SOPs enhancing work culture and productivity.Analyzed processes, identified areas for optimization, and increased efficiency.Drove initiatives promoting positive work environment and employee engagement.Gathered employee feedback to inform new policies and procedures.Worked cross-functionally to implement processes related to culture and relations.Incorporated industry best practices in organizational culture and employee relations.

Research FellowNational University of Computer and Emerging SciencesApr 2022 - May 2023Designed and implemented a Phase-Locked Loop (PLL) based tunable clock generator for ADC and DAC, providing 200MHz & 100MHz differential signals with wide tunability range and fast locking time. Utilized advanced layout techniques on TSMC 130nm, Skywater 130nm, and GF 180nm PDKs using Cadence and open-source tools.Developed an inverting delay-free insensitive switch capacitor integrator, including design, layout, DRC, LVS, PEX, and post-layout simulation verification on TSMC 130nm PDK with Cadence Tool Suite.Designed and laid out a non-overlapping clock with a 40ns period and 5ns 0-0 overlapping time on TSMC 130nm PDK.Designed and implemented a 65dB gain operational amplifier with advanced layout techniques up to GDS on TSMC 130nm and 65nm PDKs using Cadence.Utilized skills in netgen, xschem, and Cadence Virtuoso for various analog and mixed-signal integrated circuit design projects.

Mixed signal IC designing using cadence tools with gpdk(45nm)