Jun Cao Email & Phone Number

Senior Director for the analog/mixed-signal design team in Broadcom, focusing on circuits used in wireline and wireless networks. Currently leading the development of 100G/200G/400G/800G/1.2T/1.6T analog transceivers for copper and fiber links, enabling the world's fastest serdes and coherent optical modules. At same time also leading the development of wideband RF Transceivers for 5G, 5G-advanced and 6G (preliminary) base station applications. Critical blocks include transceiver data/clock path, analog filters, FFE, DFE, high-speed ADC and DAC with sampling rate ranging from a few MSps to >200GSps, high-speed high-precision data converters for 5G/6G basestation, wide-band amplifier/AGC, FIR drivers, low noise PLL, Frac-N PLL, analog and digital clock data recovery circuits. Principal driving force on the analog side for the production of 100+ communication SOCs.Over 80 US and International Patents on circuits awarded and many pending.More than 30 journal/conference publications. 20+ of them in JSSC/ISSCC, about high speed transceivers, PLLs, ADC and DACs. Almost all the industrial ICs published are in production already.Member of the Industry Advisory Board of Department of EECS in University of California, Irvine.Guest Lecturer in EECS Department of UCI.Invited speaker in ISSCC Forum and RFIC workshops.IEEE Senior MemberCustom Integrated Circuit Conference (CICC) Technical Program Committee member and conference session chair

Listed skills include Analog Circuit Design, Cmos, Analog, Pll, and 28 others.